Video-1 Block Diagram - Sony BDP-S5000ES Service Manual

Q Q
3 7 6 3 1 5 1 5 0
3-5.

VIDEO-1 BLOCK DIAGRAM

MB-124 BOARD (2/5)
IC101 (2/5)
VIDEO OUT, HDMI
C11, E10, B11,
IPIDY2-7,
F12, A10, D12, E3P_Y2-9 E3P_Y2-9
IPIDC0, IPIDC1
F11, G13
IPIDC4-7, E13, F13, E12,
IPOCLK, IPOHSB, C12, A11, E14, E3P_C2-9 E3P_C2-9
IPOVSB, IPODY0 B12, F14
E3P_VD
IPIHSB G11
E3P_HD
IPIVSB D11
E3P_VCK E3P_VCK
IPICLK C10
T E
L 1 3 9 4 2 2 9 6 5 1 3
EMMA_I2C1_SDA I2C_400k_SDA
SDA1 M27
EMMA_I2C1_SCL I2C_400k_SCL
SCL1 L27
KYOTO_XRST KYOTO_XRST
UA1CTSB J31
GLB_XRST GLB_XRST
GPIO12 F25
EMMA_CSI0_GLUE_XCS GLUE_XCS
UA1RTSB H33
EMMA_CSI0_HDE1_XCS HDE1_XCS
GPIO0 C28
EMMA_CSI0_HDE2_XCS HDE2_XCS
GPIO1 E27
EMMA_CSI0_DO
S0DOUT G30
CSI0_DI
S0DIN G33
EMMA_CSI0_CKO
S0CKOUT G31
G12, A12, E3P_ABD0-3
IPODY4-7
D17, E15
E3P_ABCK
IPODY3 F16
E3P_ALRCK
IPODY2 G15
E3P_AMCK
IPODY1 C13
E3P_ATX
IPODC0 D14
EMMA_I2C0_SDA I2CA_100k_SDA
SDA0 M28
EMMA_I2C0_SCL I2C_100k_SCL
SCL0 L28
HDMI_XRST HDMI_XRST
UA0RIB M29
HDMI_XINT HDMI_XINT
UA1DCDB H31
w w w
CEC_VP
DSP A
(SEE PAGE 3-4)
ALTERA_DONE ALTERA_DONE
.
EMMA_CSI0_DO
AUDIO
C
EMMA_CSI0_CKO
(SEE PAGE 3-7)
05
VP-062 BOARD (1/2)
CN7001 CN104
E3P_Y2-9 E3P_Y2-9
E3P_C2-9 E3P_C2-9
E3P_VD E3P_VD -> HS E3P_HS
B38 B38
E3P_HD E3P_HD -> VS E3P_VS
B36 B36
E3P_VCK E3P_VCK
B40 B40
IC101
CLOCK BUFFER
1 CLKIN CLKOUT 8
X201
20MHz
I2C_400k_SDA E3P_I2C1_SDA
A27 A27
I2C_400k_SCL E3P_I2C1_SCL
A25 A25
KYOTO_XRST KYOTO_XRST
B19 B19
GLB_XRST
A19 A19
GLUE_XCS
B11 B11
HDE1_XCS
B24 B24
HDE2_XCS
B21 B21
IC105
BUFFER
CSI_DO CSI_DO E3P_CSI0_DO
B15 B15 8 IN7 OUT7 12
CSI_DI CSI_DI E3P_CSI0_DI
B13 B13 11 OUT8 IN8 9
CSI_CK CSI_CK E3P_CSI0_CKO
B17 B17 6 IN5 OUT5 14
IC103
BUFFER
ABD0-3 ABD0-3 E3P_ABD0-3
4-7 IN3-6 OUT3-6 16-13
ABCK ABCK E3P_ABCK
A6 A6 2 IN1 OUT1 18
ALRCK ALRCK E3P_ALRCK
A8 A8 3 IN2 OUT2 17
AMCK AMCK E3P_AMCK
A4 A4 8 IN7 OUT7 12
ATX SPDIF E3P_SPDIF
A10 A10 9 IN8 OUT8 11
I2CA_100k_SDA E3P_I2C0_SDA
A23 A23
I2C_100k_SCL E3P_I2C0_SCL
A21 A21
HDMI_XRST HDMI_XRST
A17 A17
HDMI_XINT HDMI_XINT
A13 A13
CEC CEC CEC_VP
A11 A11
x a o
y
ALTERA_DONE
B20 B20
i
http://www.xiaoyu163.com
8
IC204
DIGITAL VIDEO FORMAT CONVERTER
H4, G3, E1, K16, K18,
F2, E2, D1, DT1[8-15] HD0[10-19] J16-18, J15, KYOTO_PRI_Y0-9
E3, C1 H18-15
H1, H2, J4, N18, M17, L15, M16,
H3, G1, G2, DT1[0-7] HD0[0-9] M18, L17, L16, L18, KYOTO_PRI_C0-9
F1, F3 K15, K17
KYOTO_PRI_HS
C4 DT1_HS HDMI_HS E15
KYOTO_PRI_VS
B4 DT1_VS HDMI_VS E16
KYOTO_PRI_VCK
C5 DT1_CK HDMI_CK D18
B16, A17, B18,
C656DT[0-7] C14, C15, D12, KYOTO_AUX_V00-07
C16, C17
KYOTO_AUX_HS
C656HS B14
KYOTO_AUX_VS
C656VS A15
KYOTO_AUX_VCK
C656CK B15
KYOTO_AUX_FD
C656FD A16
T1, U1, T2, U2, V2, T3, T4, U4, R4, B7, C5, B6, B5, C2, D3, D2, E2, K13,
R5, T5, R7, U5, T6, U6, R6, T7, R8, K12, J13, J12, G13, G12, F13, F12,
MDT[0-31] DDR_DATA0-31
T8, U8, V8, R9, T9, U9, T10, R10, F3, F2, G3, G2, J3, J2, K2, K3, E13,
U10, V11, U11, T11, R11, P11 D13, D12, C13, B10, B9, C9, B8
T15, V16, R14, U16, N5, N6, M6, N7,
MAD[0-11] T16, R15, V17, U17, DDR_ADD0-11 N8, M9, N9-11,
T17, U18, U15, T18 M8, L6, M7
DDR_BA0, 1
BA0, BA1 U13, U14 N4, M5
DDR_DQS0-3
P17 XTAL1 DQS[0-3] V3, V5, V7, V9 B2, H13, H2, B13
DDR_WEZ
WEZ U12 L3 /WE
Q Q
DDR_CASZ
R18 XTAL2 CASZ T12 3 7 6 L2 3 /CAS
DDR_RASZ
RASZ T13 M2 /RAS
DDR_CS1Z
B12 SDA CS1Z R13 N2 /CS
DDR_CKE
D10 SCL CKE R17 N12 CKE
DDR_CLKZ
CLKZ V14 M12 /CK
DDR_CLK
A12 RESETZ CLK V13 M11 CK
E3P_CSI0_DO
E3P_CSI0_DI
E3P_CSI0_CKO
E3P_CSI0_EDEN1_XCS
GLB_XRST
VIDEO-2
D
(SEE PAGE 3-6)
E3P_CSI0_DO
E3P_CSI0_DI
E3P_CSI0_CKO
E3P_CSI0_EDEN2_XCS
GLB_XRST
u 1 6 3
ALTERA_DONE
.
3-5
2 4
9 9
IC401
FPGA
N16, N15, F3, F4,
M18-15, G1-4, GLUE_EDEN1_Y0-9
L18-15 H1-4
T17, T16, L2, L3,
R18-15, P17, P16, M1-4, GLUE_EDEN1_C0-9
N18, N17 N1-4
GLUE_EDEN1_HS
H18 D2
GLUE_EDEN1_VS
H17 D1
GLUE_EDEN1_VCK
J16 CLK3 DPCLK1 F1
D13, C13, B13, A13,
F18-15,
D14, C14, B15, A15, GLUE_EDEN2_Y0-9
G18-15
C16, B16
D17
B10, A10, D11, C11,
D18 B11, A11, D12, C12, GLUE_EDEN2_C0-9
B12, A12
E17 DPCLK4
GLUE_EDEN2_HS
E16 D9
GLUE_EDEN2_VS
C9
IC301
GLUE_EDEN2_VCK
A9
DDR SDRAM
EDEN2_GLUE_HS
E7
EDEN2_GLUE_VS
D7
EDEN2_GLUE_VCK
DQ0-31 D8
C5, D5, A6,
B6, C6, D6, GLUE_VDAC_V00-07
A0-7, A8(AP), A9-11
A7, B7
B4
BA0, BA1
A4
DQS0-3 GLUE_VDAC_VCK
B8
1 5 1 5 0 8 9 2 4
T10
U10
GLUE_CSI0_CKO
V10
U16
KYOTO_XRST
D16
GLB_XRST
C4 DEV_CLRn
X401
27MHz
GION_VCXO_0_CLK
J3 CLK0 D4
E3P_CSI0_DO
T12
E3P_CSI0_DI
U12
E3P_CSI0_CKO VCXO_GION_0_CLK
V12 DPCLK2 B5
E3P_CSI0_GLUE_XCS
V13
GLUE_CSI1_DO
U15
GLUE_CSI1_CKO
DPCLK7 U14
GLUE_CSI1_XCS
V15
VCXO_TX_LOCK
E5
E VIDEO-2
(SEE PAGE 3-6)
VIDEO-2
F
(SEE PAGE 3-6)
m
IC403
CONFIGURATION
AND
c o
1 K17 CONF_DONE
4 DATA0 H7 2 DATA
2 C3 INT_DONE
DCLK L1 6 DCLK
nCSO J1 1 nCS
Q401, 402 ASDO K6 5 ASDI
SW3.3V J2 nCONFIG
INITIAL SWITCH
BDP-S5000ES
2
8 9 9
G VIDEO-2
(SEE PAGE 3-6)
VIDEO-2
H
(SEE PAGE 3-6)
I VIDEO-2
(SEE PAGE 3-6)
GLUE_VDAC_HS
GLUE_VDAC_VS
VIDEO-2
J
(SEE PAGE 3-6)
9 8 2 9 9
GLUE_CSI0_DO
GLUE_CSI0_DI
GLUE_CSI0_XCS
IC1003
IC1002
CLOCK
LVDS DRIVER CONDITIONER
DO1+ 7 28 OSCIN
2 DI1
DO1- 8 29 OSCIN*
IC1005
LVDS RECEIVER
N+ 3 17 CLKout1
5 OUT
N- 4 18 CLKout1*
5 DATAuWire
4 CLKuWire
6 LEuWire
12 LD
IC402
ROM