Monitor System Block Diagram - JVC GR-FXM40EK Schematic Diagrams

MONITOR SYSTEM BLOCK DIAGRAM

FROM REG
CN16 CN7601
REG_4.8V
REG_4.8V 5 20
REG_4.8V
6 21
FROM CPU
LCD_CTL
LCD_CTL 4 22
5
FROM CPU
DSP_REST
DSP_REST 18 8
PMIRROR
PMIRROR 19 7
4
FROM DSP
HDCVF
3 HDCVF
15 11
VDCVF
VDCVF 16 10
FROM CPU
RVS_SW
REV_SW 25 1
HRP1
HRP1 17 9
TO DSP
FROM DSP
2 ROUT
GOUT
BOUT
1
0 1 MAIN
A
T7501 T7501
2 6
F7501 F7501
3
4
CFL
Q7503 Q7503 Q7501 Q7501
Q7504 Q7504 Q7502 Q7502 10
1
CTL CTL OSC OSC
REG_3.2V
IC7602
R7607
L7605 5
7
6
C7617
R7612
36 34 33 31 30 29 28
37
VCO
38
39 RESET
40
COUNTER V.SYNC
MODE SEL
IC7601
PHASE
COMP
QVD
EQ
SEL
PULSE
CANCEL
48
1 2 3 4 5 6 7 8
NC
NC NC NC
Q7608
1
SW IC7604
3
LCD (DAC_3.2V)
CVF
B C
27 26 25
D7604
STH2 24
STH1 23
22
QH
H.SYNC
21
OEH
20
STV1
OEV2 18
FIELD
17
DET NC
ZOOM CPV 16
CORRECT
POL
CTL
REG_15V
INT/EXT 15
IC7602
R7604
C7609
POL 14
2
- 1
-
UD 13 3
R7601,R7602
+ +
LT R7605
12 Q7606
SW
2
CN7601
16 14 12
10 12 14
CN16
Q7001
BUF&SW
Q7002
BUF&SW
Q7003
BUF&SW
Q7003
CVF_G
BUF&SW
Q7001
CVF_R
BUF&SW
Q7005
CVF_B
BUF&SW
D E
2-51 2-52
LCD MONITOR
0 7 MONITOR
CN7602
L7604
VGH
REG_15V 9 9
VDD
L7601
REG_3.2V 8 8
VEE
11 11
MREG_4.8V
VSS
VSS(REG_-15V) 2 2
CLK1 CLK1
21 21
RL RL
13 13
CLK2 CLK2
20 20
STV2 STV2
7 7
CLK3 CLK3
19 19
STH2 STH2
12 12
STH1 STH1
24 24
Q2H Q2H
22 22
LCD MODULE
OEH OEH
23 23
STV1 STV1
3
3
OEV OEV
6 6
CPV CPV
5 5
REG_3.2V
R7645
C7622
VCOM
10 10
R7646
Q7601-Q7604
VGL
AMP 1 1
UD
4
4
R R
15 15
G G
16 16
B B
17 17
0 6 C-VF BL
TO BW/CVF
CN11
VF_BLK
VF_BLK 20 6
5
REG_4.8V
REG_4.8V 19 3
2
1
0 6 C-VF
FROM LCD/CVF CN7701
VF_COM
VF_COM 18 18
CVF_G
17
17
CVF_R
16 16
CVF_B
15
15
REG+12V
REG+12V 14 14
REG_3.2V
REG_3.2V 13 13
HDCVF
HDCVF 9 9
FROM/TO
VDCVF
VDCVF 8 8
DSP
HRP2
HRP2 7 7
CVF_CS
CVD_CS 5 5
CVF_SCK3
FROM BW/CVF 4 4
CVF_SCK3
CVF_SO3
CVF_SO3 3 3
SI3
FROM CPU SI3 2 2
BWYGAIN
FROM DSP 1 1
BWYGAIN
F
OPEN
CN7702
COM
16
GREEN
15
RED
14
BULE
13
HCK1
11
HCK2
10
LCD
HST
9
RGT MODULE
8
DWN
7
EN
6
STB
5
VCK
4
VST
3
VDD
1
G