Block Diagram - Ethernet Section - Sony HCD-CZ1 Service Manual

HCD-CZ1/NAS-CZ1
Q Q
3 7 6 3 1 5 1 5 0
6-2. BLOCK DIAGRAM – ETHERNET SECTION –
PULSE
TRANSFORMER VDDRCV
J501
38
T501 (2.5V SUPPLY)
(ETHERNET)
TXD+ 16 1
1
41 TX+
2
14 3
TXD–
2 40 TX–
NC 15
4, 5
RXD+ 11
6
3 33 RX+
7
RXD–
9 8
6 32 RX–
NC 10
7, 8
45 XO
X501
25MHz
46 XI
• R-ch is omitted due to same as L-ch.
• SIGNAL PATH
: ETHERNET
T E
L 1 3 9 4 2 2 9 6 5 1 3
EVER+3.3V
w w w
HCD-CZ1/NAS-CZ1
ETHERNET INTERFACE ETHERNET CONTROLLER
IC501 IC502
TXD0 17 79 TXD0
TXD1 18 78 TXD1
TXD2 19 77 TXD2
TXD3 20 76 TXD3
TXEN 16 80 TXEN_N
TXC/REF_CLK 15 82 TXCLK_N
TXER 14 83 TXER_N
COL/RMII 21 75 COL_N
22 74 CRS_N
CRS/RMII_LPBK
RXD0/PHYAD4 6 89 RXD0 PIOC4/SDA/SDI1 102
RXD1/PHYAD3 5 91 RXD1 PIOC5/SCL/SCLK1 101
RXD2/PHYAD2 4 92 RXD2
RXD3/PHYAD1 3 93 RXD3
RXDV/PCS_LPBK 9 87 RXDV_N
RXC 10 86 RXCLK_N
RXER/ISO 11 84 RXER_N
MDC 2 94 MDC
MDIO 1 95 MDIO
PD# 30 2 PIOC1
48 3 PIOC2
RST#
114 OSC1
X502
24.576MHz
115 OSC1N
124 OSC0
X503
11.2896MHz
125 OSC0N
+2.5V REGULATOR
+2.5V
IC506
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D/A CONVERTER
IC505
DOUT 108 2 DIN VOUTL 11
BCLK 109 3 BCKIN
MCLK 110 4 MCLK VOUTR 8 R-CH
LRCK 107 1 LRCK
PIOC7 127 17 MUTEB
PIOC0 1 18 SDIDEM
PIOC8 128
SD-RAM
IC503
8-14,16,26, MD0-15 2,3,5,6,8,9,
XD0-15 25,23-20, 11,12,39,40,42, DQ0-15
18,17 43,45,46,48,49
53-56,42-37, MA1-19 MA1-12 21-24,
A0-11
XA1-19 50,48,47,45, 27-32,
44,27,29,30,35 20,19
RAS RAS
XRASN 68 17 RAS
CAS CAS
XCASN 67 16 CAS
LDQM LDQM
XDQM0 73 14 LDQM
UDQM UDQM
XDQM1 72 36 UDQM
CLK CLK
XSDCLK 69 35 CLK
CKE CKE
XSDCKE 71 34 CKE
WE WE
XWEN 58 15 WE
CS CS
XSDCSN 70 18 CS
OE Q Q
XOEN 57
3 7 6
FLASH MEMORY
IC504
MD0-15
29-36,
DQ0-15
38-45
MA1-19
24-16,
A0-15
8-1
11 WE
28 OE
RESETN 122 12 RST
u 1 6 3
y
28 28
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2 4
8 9 9
E-LOUT
B
(Page 29)
SYSTEM CONTROLLER
IC601(2/3)
PDOWN
77 ETHER-PDOWN
IICDATA
37 I2C_DATA
IICCLK
38 I2C_CLK
3 1 5 1 5 0 8 9
NRESET
76 ETHER-NRESET
m
c o
.
2
8 9 9
2 4 9 8 2 9 9