Page 1: Table Of Contents
Development Support Third Party Development Tools DS907x SIP Stik Connectors DS5000TK User’s Guide .........
Page 2: Section 1 Introduction
USER’S GUIDE SECTION 1: INTRODUCTION The Secure Microcontroller family is a line of 8051–compatible devices that utilize nonvolatile RAM (NV RAM) rather than ROM for program storage. The use of NV RAM allows the design of a “soft” microcon- troller which provides a number of unique features to embedded system designers.
Page 3 LARGE NONVOLATILE MEMORY Soft Microprocessor chips provide nonvolatile memory control for standard CMOS SRAM. Modules combine the microprocessor chip with memory and lithium back- up. This includes conditionally write protected chip en- ables and a power supply output that switches between +5V and battery backup.
Page 4 USER’S GUIDE PRODUCT DESCRIPTION All devices listed below have the standard 8051 family feature set listed once here for convenience, but not re- peated for each device. 8051–compatible instruction set Addresses 64K program and 64K data memory Four 8–bit pseudo–bidirectional I/O ports 128 bytes scratchpad RAM Two 16–bit timer/counters One UART...
Page 5 DS2251T 128K Soft Microcontroller Module The DS2251T is a SIMM based on the DS5001. It pro- vides up to 128K bytes of on–board NV RAM and has the Byte–wide bus available at the connector. This is used with the decoded peripheral enables for memory mapped peripherals such as a UART or A/D converter.
Page 6: Section 2 Selection Guide
USER’S GUIDE SECTION 2: SELECTION GUIDE The following configurations are available. Speeds are rated maximums, but all members of the Secure Micro- CHIP DS5000FP–16 Soft Microprocessor Chip DS5001FP–16 128K Microprocessor Chip DS5002FP–16 Secure Microprocessor Chip MODULE DESCRIPTION DS5000 Soft Microcontroller Module DS5000 Soft Microcontroller...
Page 7: Section 3 Secure Microcontroller Architecture
SECTION 3: SECURE MICROCONTROLLER ARCHITECTURE Introduction The Secure Microcontroller family is based on an 8051 compatible core with a memory interface and I/O logic build around it. Many functions are identical to standard 8051s and are documented here for completeness. In general, most architecture features apply to all mem- bers of the Secure Microcontroller family.
Page 8 USER’S GUIDE SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 3–1 DRIVERS DRIVERS ENCRYPT DRIVERS DRIVERS PORT PORT 050396 7/173...
Page 9 Parallel I/O Four SFR’s provide access for the four parallel I/O port latches. These I/O ports are denoted as P0, P1, P2, and P3. A total of 32 bits of parallel I/O is available through these I/O ports. However, up to 16 bits are sacrificed when the Expanded Bus mode is used to interface to ex- ternal memory and up to six bits may be sacrificed if any external interrupt inputs, timer counter inputs, or serial...
Page 10 USER’S GUIDE Watchdog Timer When the user’s software is being executed, the Watch- dog Timer can be used to automatically restart the pro- cessor in the event that software control is lost. It is also used to generate an oscillator start–up delay to allow the clock frequency to stabilize.
Page 11: Section 4 Programmer's Guide
SECTION 4: PROGRAMMER’S GUIDE The Secure Microcontroller uses nonvolatile RAM technology for both Program and Data memory. It uses NV SRAM in place of ROM by write protecting and de- coding memory segments that a user designates as Program memory. The remaining RAM area is used as nonvolatile data storage.
Page 12 USER’S GUIDE The Scratchpad Registers are general purpose data storage RAM. They are commonly used for temporary storage of a small number of variables when high– speed access is needed. Off–chip RAM (MOVX) is used when the quantity of data is larger than 128 bytes. The Scratchpad Registers are lithium backed and will be preserved in the absence of power.
Page 13 The 8051 instruction set allows efficient (single cycle) access to variables when using the Working Registers. These are a group of four 8–byte banks of Scratchpad RAM. The active Working Registers are referred to as R0–R7. They reside between location 00h and 1Fh, de- pending on which bank is currently selected.
Page 14 USER’S GUIDE DS5000 Series Memory Organization As mentioned above, the DS5000 series consists of the DS5000FP chip and the DS5000(T) and DS2250T mod- ules. The programming model discussed in this section applies to all of these parts. The DS5000 series Byte– wide bus has 15 address lines, eight data lines, a R/W strobe, and two chip enables to access nonvolatile RAM.
Page 15 DS5000 SERIES MEMORY MAP Figure 4–3 FFFFh 7FFFh 1FFFh PARTITION ADDR. BYTE–WIDE BUS ACCESS 0000 PROGRAM MEMORY LEGEND: Ñ Ñ = NO MEMORY ACCESS Ñ Ñ BYTE–WIDE ACCESS WITH CE2 (NONVOLATILE RAM) BYTE–WIDE ACCESS WITH CE1 (NONVOLATILE RAM) Ï Ï = EXPANDED BUS ACCESS ON PORTS 0 AND 2 Ï...
Page 16 USER’S GUIDE case is to select a Range of 8K, and to choose a Parti- tion of greater than 8K. This will result in the Range as the limiting factor. Addresses above the Range will auto- matically be deflected to the Expanded bus. No data memory will be allocated in NV RAM for this configura- tion.
Page 17 MCON.3: RA32/8 “Range Address”: Sets the maximum usable address on the Byte–wide bus. RA32/8 = 0 sets Range Address = 1FFFH (8K); RA32/8 = 1 sets Range Ad- dress = 7FFFH (32K) Initialization: Set to a 1 on a No V cleared to a 0 from a previous 1 state.
Page 18 USER’S GUIDE a Partitionable mode (PM=0), the DS5001 can use up to 64K x 8 SRAM for program and data on its Byte–wide bus. It can partition this area into program and data segments on 4K boundaries. The 64K memory space would consist of two 32K x 8 SRAMs.
Page 19 PARTITIONABLE MEMORY MAP FOR DS5001/DS5002 SERIES Figure 4–5 FFFFh PARTITION ADDR. 0000 LEGEND: BYTE–WIDE ACCESS (NONVOLATILE RAM) Ï Ï = EXPANDED BUS ACCESS ON PORTS 0 AND 2 Ï Ï The non–partitionable mode allows the maximum amount of memory to be used on the Byte–wide bus. A non–partitionable mode would be used because the 8051 architecture is restricted to a total of 64K program and 64K data (without bank switching).
Page 20 USER’S GUIDE Any address that does not fall into the Byte–wide bus area is routed to the Expanded bus of Ports 0 and 2. This could only occur for the first two settings. Note that a single 128K device is the least expensive in terms of component cost and size.
Page 21 On occasion, a memory mapped peripheral is needed that interfaces directly to an 8051 multiplexed bus. When this occurs, MOVX instructions can be forced to use the Expanded bus in any mode with the EXBS bit (RPCTL.5). Setting this bit to a logic one forces all PERIPHERAL ENABLES IN THE DATA MEMORY MAP Figure 4–7 DS5001/DS5002 Memory Map Control Like the DS5000, the DS5001/DS5002 uses Special...
Page 22 USER’S GUIDE DS5001/DS5002 SERIES MCON REGISTER Figure 4–8 Bit Description: MCON.7–4: PA3–0 Partition Address. When PM=0, this address specifies the boundary between program and data memory in a continuous space. Initialization: Unaffected by watchdog, external, or power–up resets. Set to 1111B on a No V Read Access: Can be read normally at any time.
Page 23 DS5001/DS5002 SERIES RPCTL REGISTER BITS AFFECTING MEMORY Figure 4–9 ––– Bit Description: RPCTL.5: EXBS The Expanded Bus Select routes data memory access (MOVX) to the Expanded bus formed by ports 0 and 2 when set. Initialization: Cleared after all resets. Read Access: Can be read at any time.
Page 24 USER’S GUIDE Application software always has unrestricted read/write access to the nonvolatile RAM designated as data memory. This is the memory that lies above the Partition address and below the Range address (the non–parti- tionable configuration of the DS5001 will be addressed separately).
Page 25 TA, #0AAh TA, #55h MCON, #10001010b TA, #0AAh TA, #55h MCON, #11001000b ; LOAD NEW PARTITION AND CLEAR PAA BIT RELOADING PORTIONS OF A DS5000 SERIES DEVICE Figure 4–10 7FFFh DATA MEMORY SPACE 6000h 4000h PROGRAM 0800h MEMORY SPACE 0000h BEFORE LOADING PAA=0 PA3–0=1000b...
Page 26 USER’S GUIDE SOFT RELOAD OF A DS5001/DS5002 When application software decides that it should repro- gram a portion of memory, the software must convert the target area into data memory. However, a Soft Re- load of a DS5001 series device has minor variations from the DS5000 version.
Page 27 RELOADING A DS5001/DS5002 SERIES DEVICE Figure 4–11 FFFFh DATA MEMORY SPACE A000h 4000h PROGRAM 1000h MEMORY SPACE 0000h BEFORE LOADING PA3–0=0100b LEGEND: NONVOLATILE RAM PROGRAM MEMORY NONVOLATILE RAM DATA MEMORY TA, #0AAh TA, #55h ; TIMED ACCESS 2 MCON, #00011000b ; SET PARTITION TO 1000h ;...
Page 28 USER’S GUIDE Special Function Registers The Secure Microcontroller uses Special Function Reg- isters (SFRs) to control most functions. In many cases, an SFR will contain 8 bits, each of which control a func- tion or report status on a function. The SFRs reside in register locations 80–FFh.
Page 29 DS5000 SERIES SPECIAL FUNCTION REGISTER MAP Figure 4–12 DIRECT BYTE ADDRESS (MSB) 0F0H 0E0H 0D0H 0C7H 0C6H 0B8H – 0B0H 0A8H – 0A0H GATE SMOD * BITS IN ITALICS ARE NONVOLATILE BIT ADDRESS NOT BIT ADDRESSABLE RA32/8 ECE2 NOT BIT ADDRESSABLE –...
Page 30 USER’S GUIDE DS5001/DS5002 SERIES SPECIAL FUNCTION REGISTER MAP Figure 4–13 DIRECT BYTE ADDRESS (MSB) 0F0H 0E0H 0DAH ––– 0D8H 0D0H 0CFH 0C7H 0C6H 0C3H 0C2H RNGE3 RNGE2 0C1H 0B8H ––– 0B0H 0A8H ––– 0A0H GATE SMOD * BITS IN ITALICS ARE NONVOLATILE 050396 29/173 BIT ADDRESS NOT BIT ADDRESSABLE...
Page 31 POWER CONTROL REGISTER Label: PCON SMOD Bit Description: PCON.7 SMOD “Double Baud Rate”: When set to a 1, the baud rate is doubled when the serial port is being used in modes 1, 2, or 3. Initialization: Cleared to a 0 on any reset. Read Access: Can be read normally at any time.
Page 32 USER’S GUIDE PCON.3: EPFW “Enable Power Fail Interrupt”: Used to enable or disable the Power Fail Interrupt. When EPFW is set to a 1, it will be enabled; it will be disabled when EPFW is cleared to a 0. Initialization: Cleared to a 0 on any type of reset.
Page 33 TIMER CONTROL REGISTER Label: TCON Bit Description: TCON.7: “Timer 1 Overflow Flag”: Status bit set to 1 when Timer 1 overflows from a previous count value of all 1’s. Cleared to 0 when CPU vectors to Timer 1 interrupt service routine. Initialization: Cleared to 0 on any type of reset.
Page 34 USER’S GUIDE TCON.0: “Interrupt 0 Type Select”: When set to 1, 1–to–0 transitions on INT0 will be used to generate interrupt requests from this pin. When cleared to 0, INT0 is level–activated. Initialization: Cleared to a 0 on any type of reset. TIMER MODE REGISTER Label: TMOD GATE...
Page 35 SERIAL CONTROL REGISTER Label:SCON Bit Description: SCON.7, SCON.6: SM0, SM1 “Mode Select”: Used to select the operational mode of the serial I/O port as follows: MODE Mode 0 Mode 1 Mode 2 Mode 3 Initialization: Cleared to 0 on any type of reset. SCON.5: “Multiple MCU Comm”: Used to enable the multiple microcontroller communications feature for...
Page 36 USER’S GUIDE Initialization: Cleared to a 0 on any type of reset. SCON.0: “Receive Interrupt”: Status bit used to signal that a serial data word has been received and loaded into the receive buffer register. In mode 0, it is set at the end of the 8th bit time.
Page 37 INTERRUPT PRIORITY REGISTER Label:IP – Bit Description: IP.7: “Reset Watchdog Timer”: When set to a 1, the Watchdog Timer count will be reset and counting will begin again. The RWT bit will then automatically be cleared again to 0. Writ- ing a 0 into this bit has no effect.
Page 38 USER’S GUIDE DS5001 CRC REGISTER Label: CRC RNGE3 RNGE2 RNGE1 Bit Description: CRC.7–4 RNGE3–0 Determines the range over which a power–up CRC will be performed. Addresses are specified on 4K boundaries. Initialization: Reset to 0 on a No V Read Access: Can be read at any time.
Page 39 DS5000 MEMORY CONTROL REGISTER Label:MCON Bit Description: MCON.7–4: PA3–0 “Partition Address”: Used to select the starting address of Data Memory on the Byte–wide bus. Program space lies below the partition address. *A 4K byte increment (not 2K bytes) in the Partition Address takes place between bit field values 1110B and 111B.
Page 40 USER’S GUIDE Read Access: May be read normally anytime. Write Access: Cannot be modified by the application software; can only be written via the Bootstrap Loader. MCON.2: ECE2 “Enable Chip Enable 2”: Used to enable or disable the CE2 signal for the Byte–wide bus data memory.
Page 41 Write Access: Timed Access Protected. Cannot be written by the application software if set to 0000B by the serial loader. If a 0000B is written via the serial loader and the security lock is set, the Partition will become 1111B. The same will occur if write access is available and application software writes a 0000B.
Page 42 USER’S GUIDE PROGRAM STATUS WORD REGISTER Label:PSW All of the bits in PSW except parity are read/write and are cleared to 0 on any type of reset. The Parity bit is read only and is cleared to 0 on any type of reset. Bit Description: PSW.7: “Carry”:...
Page 43 DS5001/DS5002 RPC CONTROL REGISTER Label: RPCTL ––– Bit Description: RPCTL.7 When internal hardware sets this read–only bit to a 1, a new value may be read from the random number generator register of the DS5001/DS5002 (RNR;0CFh). This bit is cleared when the random number is read, and approximately 160 s are required to generated the next number.
Page 44 USER’S GUIDE Read Access: Can be read anytime. Write Access: Can be written when the RPC mode is enabled (RPCON=1). RPCTL.1 RPCON Enable the RPC 8042 I/O protocol. When set, port 0 becomes the data bus, and port 2 becomes the control signals. Initialization: Cleared on all resets.
Page 45 Read Access: Can be read by DS5001/DS5002 and host CPU when in RPC mode. Write Access: Can be written by the DS5001/DS5002 when in RPC mode. RPS.1: Input Buffer Full Flag is set following a write by the external host, and is cleared following a read of the DBBIN by the DS5001/DS5002.
Page 46 USER’S GUIDE INSTRUCTION SET Introduction The Secure Microcontroller executes an instruction set which is object code compatible with the industry stan- dard 8051 microcontroller. As a result, software tools written for the 8051 are compatible with the Secure Microcontroller, including cross–assemblers, compil- ers, and debugging tools.
Page 47 The 16–bit DPTR register may be used to access any Data Memory location within the 64K byte space. MOVX @DPTR,A ; Load the Data Memory location ; pointed to by the contents of the ; DPTR register with the contents ;...
Page 48 USER’S GUIDE Program Status Flags All of the Program Status flags are contained in the PSW register. Instructions which affect the states of the flags are summarized below. INSTRUCTIONS THAT AFFECT FLAG SETTINGS INSTRUCTION ADDC SUBB SETB C LEGEND: 0 = Cleared to 0 1 = Set to a 1 = Modified according to the result of the operation.
Page 49: Section 5 Memory Interconnect
RECOMMENDED SRAMs FOR USE WITH SOFT MICROCONTROLLERS Table 5–1 RAM SIZE VENDOR 8K x 8 Dallas 8K x 8 Sharp 32K x 8 Hitachi 32K x 8 Mitsubishi 32K x 8 Sony 32K x 8 Sony 128K x 8 Hitachi 128K x 8 Mitsubishi 128K x 8...
Page 50: Real Time Clock
USER’S GUIDE MEMORY INTERCONNECT OF THE DS5000FP Figure 5–1 DS5000FP Ç Ç Ç Ç Ç BA14–BA0 PORT0 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç PORT1 BD7–BD0 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç...
Page 51 The DS5001FP has several memory options. It can be connected to between one 8K byte SRAM and four 32K byte SRAMs. It will also support one 128K byte SRAM. In most cases the DS5001FP is used for its greater memory access so it will not be used with 8K RAMs.
Page 52 USER’S GUIDE MEMORY INTERCONNECT OF THE NON–PARTITIONABLE DS5001FP, DS5002FP Figure 5–4 DS5001FP/DS5002FP Ç Ç Ç Ç Ç Ç PORT0 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç PORT1 Ç Ç Ç Ç Ç Ç Ç Ç Ç...
Page 53 MEMORY INTERCONNECT USING THE 128K SRAM Figure 5–5 DS5001FP/DS5002FP Ç Ç Ç Ç Ç PORT0 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç PORT1 Ç Ç Ç Ç Ç Ç Ç Ç Ç PORT2 Ç Ç Ç Ç Ç...
Page 54 USER’S GUIDE DS2251T–128 BLOCK DIAGRAM Figure 5–6 DS2251T 72 PINS Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ç Ç PORT0 Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ó Ç...
Page 55 DS2252T–32 BLOCK DIAGRAM Figure 5–7 DS2252T 40 PINS Ç Ç Ç PORT0 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç PORT1 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç PORT2 Ç...
Page 56: Section 6 Lithium/Battery Backup
USER’S GUIDE SECTION 6: LITHIUM/BATTERY BACKUP Soft Microcontroller devices are lithium backed for data retention in the absence of V . In the Soft Microcon- troller the state of the microcontroller is also maintained, unlike a conventional processor system using an exter- nal NV RAM.
Page 57 POWER SUPPLY SLEW RATE Figure 6–1 40 s, 130 s CCMIN LITHIUM CURRENT Each time V is restored, the lithium backed functions will remain as they were left. A result is that many of these values are not altered on a reset condition except for the ‘no battery reset’.
Page 58 USER’S GUIDE 10 years depending on the user’s actual environment and design goals. The system lifetime can be determined from three parameters: 1) Data retention current, 2) Lithium cell capacity, 3) Lithium self–discharge. Current production lithium cells have extremely good self–discharge per- formance.
Page 59 LITHIUM BATTERY USAGE In the vast majority of applications, lithium batteries pro- vide a reliable means of backing up data and configura- tion. The voltage varies only slightly over its useful life, so it is difficult to measure capacity. A CR chemistry will begin life at 3.3V and drop to 2.9V near the end of life.
Page 60: Section 7 Power Management
USER’S GUIDE SECTION 7: POWER MANAGEMENT Introduction All Dallas Semiconductor microcontrollers are imple- mented using fully static CMOS circuitry for low power consumption. Power consumption is a linear function of crystal frequency. Two software initiated modes are available for further power saving at times when proces- sing is not required and V is at normal operating volt- age.
Page 61 Write Access: Cannot be written. PCON.3: EPFW “Enable Power Fail Interrupt”: Used to enable or disable the Power Fail Interrupt. When EPFW is set to a 1, it will be enabled; it will be disabled when EPFW is cleared to a 0. Initialization: Cleared to a 0 on any type of reset.
Page 62 USER’S GUIDE The original contents of those Special Function regis- ters that are initialized by a reset are lost. Voltage Monitoring Circuitry The on–chip voltage monitoring circuitry automatically places the microprocessor in its Data Retention state in the absence of V .
Page 63 Power Fail Interrupt When V is stable, program execution proceeds as normal. If V should decay from its nominal operating voltage and drop to a level below the V then the internal PFW status flag (PCON.5) will be set. In addition, a Power Fail Warning interrupt will be gener- ated if it has been enabled via the EPFW control bit (PCON.3).
Page 64 USER’S GUIDE threshold, the Power On Reset cycle will be executed as before. As a result, no special processing is required in software to accommodate this case. In the case that V dips without going below V PFW flag will be set and a Power Fail Warning interrupt will still occur when V drops below the V old.
Page 65: Section 8 Software Control
SECTION 8: SOFTWARE CONTROL Introduction Several features have been incorporated into the Secure Microcontroller to help insure the orderly execu- tion of the application software in the face of harsh elec- trical environments. Any microcontroller which is oper- ating in a particularly noisy environment is susceptible to loss of software control.
Page 66 USER’S GUIDE This code allows the reset of the Watchdog Timer: SETB The Watchdog Timer bit may have been set using ORL IP, #80H which takes two cycles. This code allows the reset of the Watchdog Timer using a different ap- proach: Note that a new value for IP could have been retrieved from any direct register instead of the current IP.
Page 67 Timed Access provides a statistical protection. It is unlikely that randomly generated states will correctly match the sequence and timing required to bypass the Timed Access logic. Presented below is a brief justifica- tion for each bit that is protected by Timed Access. The EWT bit is protected to prevent errant software from disabling the Watchdog Timer.
Page 68 USER’S GUIDE During subsequent program execution, the Watchdog Timer can be reset by a Timed Access write operation which sets the RWT bit to a 1. This will cause the Watch- dog Timer to begin counting machine cycles again from an initial count of 0.
Page 69 WATCHDOG TIMER CONTROL BITS Bit Description: PCON.4: “Watchdog Timer Reset” Set to a 1 when a Watchdog Timer timeout occurs. If Watchdog Timer Reset is enabled, this will indicate the cause of the reset. Cleared to 0 immediately following a read of the PCON register. Initialization: Set to a 1 after a Watchdog Timeout.
Page 70 USER’S GUIDE blocks over which the CRC calculation is performed. For example, if the nibble is set to 0001b, the CRC range is from 0000 to 0FFFh. Once the LSB of the CRC regis- ter is set, the loader “I” command will cause the CRC of the specified block to be computed.
Page 71 CRC CODE EXAMPLE Figure 8–3 This routine tests the CRC–16 circuit in the DS5001FP crcmsb crclsb begin: end_loop: sjmp As mentioned, the CRC–16 function is optionally avail- able to the application software. This is available regardless of whether the automatic power–on CRC is used.
Page 72: Section 9 Firmware Security
USER’S GUIDE SECTION 9: FIRMWARE SECURITY One of the most unique features of the Secure Micro- controller is its firmware security. The family far sur- passes the standard offering of ROM based microcon- trollers in keeping system attackers or competitors from viewing the contents of memory.
Page 73 SECURITY LOCK Ordinarily, the easiest way to dump (view) the memory contents of a Secure Microcontroller is using the Boot- strap Loader. On request, the Loader will transfer the contents of memory to a host PC. This is prevented by the Security Lock.
Page 74 USER’S GUIDE DS5000 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 9–1 PROGRAM DATA COUNTER POINTER SECURE INTERNAL ADDRESS BUS BOOTSTRAP LOADER SECURITY LOCK SECURE INTERNAL DATA BUS DS5002 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 9–2 PROGRAM DATA COUNTER POINTER SECURE INTERNAL ADDRESS BUS RANDOM NUMBER GENERATOR...
Page 75 In a DS5000, the encryption feature is optional. A DS5000 can be locked irrespective of its encryption and encrypted irrespective of the lock. Neither makes much sense by itself. The encryption process is enabled by loading an Encryption Key for the first time. Prior to load- ing a Key, the DS5000 remains in a non–encrypted state.
Page 76 USER’S GUIDE Encryption Algorithm The Secure Microcontroller family uses a proprietary algorithm to encrypt memory. The DS5000FP and DS5002FP use different encryption algorithms. They are the result of improvements made over time in the proprietary encryptor circuits. The original DS5000FP (circa 1988) has the first version of encryptor.
Page 77 Dummy Bus Access The Secure Microcontroller makes its memory contents obscure through encryption. Additional steps are also to prevent analysis of the bus activity by 8051–familiar hackers. Both the DS5000FP and DS5002FP insert dummy memory operations when possible. In the 8051 architecture, there are typically two identical memory accesses per instruction cycle, but most operations so nothing with the second program fetch.
Page 78 USER’S GUIDE On–chip Vector RAM A 48–byte RAM area is incorporated inside the DS5000FP and DS5002FP. This area maps to the first 48 locations of program memory to store reset and interrupt vectors. Any other data stored in the first 48 locations will be contained in this Vector RAM.
Page 79 Security Summary by Part The preceding information outlined each of the security features. Their inclusion in various parts is shown in the table at the beginning of this chapter. For completeness, the following is a summary description of security fea- tures for each part in the Secure Microcontroller Family.
Page 80 USER’S GUIDE APPLICATION: ADVANCED SECURITY TECHNIQUES The Secure Microcontroller family has been used for numerous applications requiring security. Different lev- els of security are required depending on the sensitivity of the application and the value of the protected informa- tion. As mentioned above, the goal of the microcontrol- ler security is to make stealing the protected information more difficult than the information is worth.
Page 81 Change Code Perhaps most importantly, the user should reprogram portions of the Secure Microcontroller that deal with se- curity. For example, if the microprocessor is performing DES, the user can change DES keys. Any security sys- tem can be broken with enough time and resources. By altering the security features, this threat can be mini- mized.
Page 82: Section 10 Reset Conditions
USER’S GUIDE SECTION 10: RESET CONDITIONS Reset Sources The Secure Microcontroller family is designed to pro- vide proper reset operation with a minimum of external circuitry. In fact, for may applications, external reset cir- cuitry is not required. The possible sources of reset are as follows: a) Power On (operating voltage applied to V b) No V...
Page 83 SPECIAL FUNCTION REGISTER RESET STATES Table 10–1 REGISTER DPTR P0–P3 TMOD TCON SCON SBUF PCON MCON (DS5000) MCON (DS5001) Encryption Key (DS5000) RPCTL (DS5001) Status (DS5001) RNR (DS5001) CRC (DS5001) CRC High (DS5001) CRC Low (DS5001) NOTES: X indicates a bit that is indeterminate on a reset. U indicates a bit that is unchanged from its previous state on a reset.
Page 84 USER’S GUIDE Power On Reset The Secure Microcontroller family provides an internal Power On Reset capability which requires no external components. When voltage is applied to the V from a power off condition, the device automatically per- POWER ON RESET TIMING Figure 10–2 CLOCK OSC.
Page 85 No–V Power On Reset During a Power On Reset cycle, a test is automatically performed by the internal control circuitry to measure the voltage of the lithium power source. This test deter- mines whether or not the voltage (V mum level required (V ) to insure that the nonvolatile LImin areas can be maintained in the absence of V...
Page 86 USER’S GUIDE APPLICATION: RESET ROUTINE EXAMPLE Like the 8051, Dallas Semiconductor Microcontrollers will begin execution at address 0000h. This is the Reset Vector, followed by other vector locations used for inter- rupts. These are discussed in the section covering inter- rupt operation.
Page 87 A code example that initializes the memory map is as follows. It assumes that the DS5000FP user requires a MCON 0C6h SJMP Start Start : #0AAh #55h MCON, #02h MCON, #0B8h #0AAh #55h MCON, #0FDh Another common memory requirement is the initializa- tion of the Data Pointer.
Page 88 USER’S GUIDE Timers The microprocessor disables timer activity (excluding the Watchdog) and serial port communication on a re- set. Therefore, each timer must be setup and enabled as part of the reset routine. The serial port mode must also be initialized if used. This is covered in detail in the User’s Guide section on Timers and Serial I/O respec- SJMP Start...
Page 89: Section 11 Interrupts
SECTION 11: INTERRUPTS The Secure Microcontroller family follows the standard 8051 convention for interrupts (with one extra) and is fully compatible. An interrupt stops the normal flow of processing and allows software to react to an event with special processing. This event can be external, time–re- lated, or the result of serial communication.
Page 90 USER’S GUIDE External Interrupts The two external interrupts are INT0 and INT1. They correspond to P3.2 and P3.3 respectively. These pins become interrupts when the respective interrupt is enabled. Otherwise, they are simply port pins. No other special action is required. Each pin is sampled once per machine cycle when the interrupts are enabled.
Page 91 global enable bit. It can only be enabled or disabled using the EPFW bit. Simulated Interrupts Except for PFW, any interrupt can be forced by setting the corresponding flag to a logic 1 in software. This INTERRUPT REQUEST SOURCES Figure 11–1 INT0 TIMER 0 OVERFLOW...
Page 92 USER’S GUIDE INTERRUPT ENABLE CONTROL BITS Figure 11–2 Bit Description: All bits are read/write at any time and are cleared to 0 following any hardware reset. IE.7: “Enable All Interrupts”: When set to 1, each interrupt except for PFW may be individually enabled or disabled by setting or clearing the associated IE.x bit.
Page 93 INTERRUPT PRIORITIES The Secure Microcontroller provides a three priority interrupt scheme. Multiple priority levels allow higher priority sources to interrupt lower priority ISRs. The Power–fail Warning Interrupt automatically has the highest priority if enabled. The remaining interrupts can be programmed by the user to either high or low priority. The priority scheme woks as follows.
Page 94 USER’S GUIDE INTERRUPT ACKNOWLEDGE The various interrupt flags are sampled an latched once every machine cycle, specifically during clock phase S5P2 (see CPU timing section) regardless of other in- terrupt related activity. Likewise, the latched states of the flags are polled once every machine cycle for the sampling which took place during the previous machine cycle.
Page 95 cycle. If the interrupt acknowledge does not take place for one of the reasons cited above, the request flag will become subsequently inactive and the interrupt will have been lost and will not be serviced. When an interrupt request is acknowledged, a long call is executed to the interrupt vector location and the 2–byte return address is pushed onto the stack.
Page 96: Section 12 Parallel I/O
USER’S GUIDE SECTION 12: PARALLEL I/O OVERVIEW The Secure Microcontroller provides four 8–bit bidirec- tional ports for general purpose I/O functions. Each port pin is bit and byte addressable using four SFRs that con- trol the respective port latch. Each bit has an associated latch (accessed via SFR), input buffer circuit, and output driver circuit.
Page 97 PORT 1 FUNCTIONAL CIRCUITRY INTERNAL DATA BUS WRITE ENABLE READ ENABLE PORT 2 FUNCTIONAL CIRCUITRY ADDRESS A8–A15 INTERNAL DATA BUS WRITE ENABLE READ ENABLE DELAY = 2Tclk READ LATCH/PIN ADDRESS CONTROL DELAY = 2Tclk READ LATCH/PIN USER’S GUIDE PORT POWER DOWN PORT POWER...
Page 98 USER’S GUIDE PORT 3 FUNCTIONAL CIRCUITRY RXD, TXD WR, RD INPUTS INTERNAL DATA BUS WRITE ENABLE READ ENABLE SERIAL TIMER AND INTERRUPT INPUTS OUTPUT FUNCTIONS Slightly different output buffer structures are implement- ed for the four parallel I/O ports. When the pins are used strictly for parallel I/O, ports 1, 2, and 3 have internal weak pull–up devices.
Page 99 least significant eight bits of address and data. When 1’s are output on Port 2 for address bits during these cycles, strong current drivers are employed. The information in the Port 2 SFR latch is unchanged during these cycles. PARALLEL PORT OUTPUT BUFFERS (PORTS 1, 2, AND 3) Figure 12–2 Q FROM PORT LATCH INTERNAL...
Page 100 USER’S GUIDE READ–MODIFY–WRITE INSTRUCTIONS MNEMONIC DJNZ MOV PX.n,C CLR PX.n SETB PX.n Read–Modify–Write instructions input the state of the latch rather than the pin so that the operation takes place on the value which was originally written to the latch by the software. REPROGRAMMABLE PERIPHERAL CONTROLLER (RPC) The Reprogrammable Peripheral Controller (RPC)
Page 101 USE OF THE RPC MODE Figure 12–3 CONTROL BUS DATA BUS USE OF THE RPC MODE Figure 12–4 RPC INTERRUPTS RPC mode provides an additional interrupt to the stan- dard Secure Microcontroller set. An Input Buffer Full Interrupt (IBF) will be performed (if enabled) when data is written to the DBBIN from a host.
Page 102 USER’S GUIDE RPC STATUS REGISTER – STATUS (ADDRESS 0DAH) Figure 12–5 Bit Description: RPS.7–4: General purpose status bits that can be written by the DS5001/2 and can be read by the external host. Initialization: Cleared when RPCON=0. Read Access: Can be read by the DS5001/2 and host CPU when RPC mode is invoked. Write Access: Can be written by the DS5001/2 when RPC mode is invoked.
Page 103 RPC PROTOCOL Data is written to the microprocessor by the host CPU and is placed in the DBBIN. At this time, the IBF flag is set in the RPC Status Register. If enabled by the IBI bit in the RPCTL register, an IBI interrupt will occur. No fur- ther updates of the DBBIN will be allowed until the buffer is read by the microprocessor.
Page 104 USER’S GUIDE RPC CONTROL REGISTER – RPCTL (ADDRESS 0D8H) Figure 12–6 – EXBS Bit Description: RPCTL.3: When using the RPC mode, an interrupt may be required for the Input Buffer Flag. This interrupt is enabled by setting the Input Buffer Interrupt (IBI) bit. At this time, the timer 1 interrupt is disabled, and this RPC mode interrupt is used in its place (vector location 1BH).
Page 105: Section 13 Programmable Timers
SECTION 13: PROGRAMMABLE TIMERS FUNCTIONAL DESCRIPTION The Secure Microcontroller incorporates two 16–bit tim- ers called Timer 0 and Timer 1. Both can be used to gen- erate precise time intervals, measure external pulse widths, or count externally applied pulses. Each programmable timer operates either as a “timer” in which time periodic interrupts may be generated or as a “counter”, in which the timer register is incremented when transitions are detected on an external input pin.
Page 106 USER’S GUIDE TMOD.5, TMOD.4: Timer 1 Mode Control “Mode Select” These bit select the operating mode of the associated timer/counter as fol- lows: Initialization: Cleared to 0 on any reset. TMOD.1, TMOD.0: Timer 0 Mode Control “Mode Select” These bit select the operating mode of the associated timer/counter as fol- lows: Initialization: Cleared to 0 on any reset.
Page 107 Mode 0 Figure 13–3 is a block diagram of a timer/counter oper- ating in Mode 0. Mode 0 configures either program- mable timer for operation as a 13–bit timer/counter. For Timer 0, selection of Mode 0 configures bit 4 – 0 of TL0 as bits 4 –...
Page 108 USER’S GUIDE Mode 1 Mode 1 for both programmable timers operates in an identical fashion described for Mode 0, except Mode 1 configures a 16–bit timer/counter register. In this case, for Timer 0, TH0 contains the most significant eight bits of the count value while TL0 holds the least significant eight bits.
Page 109 Mode 3 When Timer 0 is selected for operation in Mode 3, both TH0 and TL0 are configured independently as an 8–bit timer/counter and as an 8–bit timer. Figure 13–5 illus- trates the function of Timer 0 for Mode 3 operation. For Timer 0 in Mode 3, TL0 becomes an 8–bit timer/ counter which is controlled by the Timer 0 control bits (TR0 and TF0) in the TMOD and TCON registers.
Page 110: Section 14 Serial I/O
USER’S GUIDE SECTION 14: SERIAL I/O FUNCTION DESCRIPTION The Secure Microcontroller, like the 8051, includes a powerful Serial I/O (UART) port capable of both syn- chronous and asynchronous communication. The baud rate and time–base source is fully programmable. The serial port uses P3.0 as Receive Data (RXD) and P3.1 Transmit Data (TXD).
Page 111 value that generates the required time interval at its overflow. This is the most common mode of communi- cating with a PC COM port or similar device. When talk- ing to a PC in Mode 1, the PC would be set to 8–N–1 ( 8 bits, no parity, 1 stop).
Page 112 USER’S GUIDE SCON.2: “Rcv. Bit 8”: Indicates the state of the 9th data bit received while in Mode 2 or 3 operation. If Mode 1 is selected with SM2=0, RB8 is the state of the stop bit which was received. RB8 is not used in Mode 0. Initialization: Cleared to a 0 on any type of reset.
Page 113 In most applications, Timer 1 will be configured as a tim- er which uses the internal clock oscillator frequency as its clock source. The baud rate will then be divided down from the time base applied to the XTAL1 and XTAL2 pins.
Page 114 USER’S GUIDE was originally written into bit position D8. During the final shift register operation, another 0 is shifted in from the left so that the Transmit Shift register contains all 0’s. Also at this time, the Transmit Interrupt flag (TI) is set and a serial interrupt will be generated if enabled.
Page 115 MODE 0 BLOCK DIAGRAM AND TIMING Figure 14–2 LOAD OSC. RDSBUF LDSBUF LDSBUF DIV. BY FLAG FLAG SERIAL INTERRUPT TRANSMIT TIMING: LDSBUF SHIFT SHCLK (TXD) (DATA OUT) RECEIVE TIMING: WRSCON (Ri=0) SHCLK (TXD) SHIFT (DATA IN) OUTPUT SHIFT REGISTER D7 D6 D5 D4 D3 D2 SHIFT RDSBUF...
Page 116 USER’S GUIDE ASYNCHRONOUS OPERATION Mode 1, 2, and 3 provide asynchronous, full-duplex communication via the Serial I/O Port. The serial data word is either 10 or 11 bits long, depending on the mode selected. All three modes include one start bit, eight data bits, and one stop bit.
Page 117 ware. In an overrun condition with RI=1, the originally re- ceived word will remain in the Receive Data Buffer and all successively received data words will be lost. When SM2=1, received data words will be selectively discarded in a manner depending on the asynchronous mode selected.
Page 118 USER’S GUIDE SERIAL PORT MODE 1 BLOCK DIAGRAM Figure 14–3 TIMER 1 OVERFLOW WRSBUF RDSBUF SMOD WRSBUF DIVIDE SCLK BY 16 RESET FLAG FLAG SERIAL INTERRUPT TRANSMIT TIMING: WRSBUF SHIFT RECEIVE TIMING: BIT DETECTOR SAMPLING SHIFT 050396 117/173 XMIT SHIFT REGISTER LOAD SHIFT RDSBUF...
Page 119 MODE2 AND 3 BLOCK DIAGRAM Figure 14–4 LOAD CLOCK WRSBUF RDSBUF WRSBUF DIVIDE SCLK BY 16 RESET FLAG FLAG SERIAL INTERRUPT TRANSMIT TIMING: WRSBUF SHIFT RECEIVE TIMING: BIT DETECTOR SAMPLING SHIFT XMIT SHIFT REGISTER SHIFT RDSBUF LOAD SI0 CONTROL DIV. DETECTOR USER’S GUIDE P3.1...
Page 120 USER’S GUIDE APPLICATION: SERIAL PORT INITIALIZATION The serial port can provide either synchronous or asynchronous serial communication. This note demon- strates how to initialize the serial port and includes an example showing how to perform asynchronous com- munication with a PC COM port. A typical goal of microcontroller to PC communication is to transfer stored data from the nonvolatile RAM.
Page 121 SM0 = 0 and SM1 = 1 corresponds to the value SCON.7 = 0 and SCON.6 = 1. In addition the since the applica- tion requires receiving data, the serial receiver must be SCON – 98h This application uses the serial interrupt. It serves two purposes.
Page 122 USER’S GUIDE This formula solves as : 32 * 12 t For 9600 = Baud rate, TH1 = FDh with SMOD = 0. To create 19,200 baud, the SMOD bit should be set to a logic 1 with the same value for TH1. SMOD has the effect of doubling the baud rate for any time out value.
Page 123 ;This code example shows how to initialize the serial port and transmit / ; receive code as described above. MCON Reset : SJMP Start Serial_ISR : RETI Start : TA, #0AAh TA, #55h MCON, #88h SCON, #50h TMOD, #20h TCON, #40h TH1, #0FDh PCON, #7Fh IP, #10h...
Page 124: Section 15 Cpu Timing
USER’S GUIDE SECTION 15: CPU TIMING OSCILLATOR The Secure Microcontroller provides an on–chip oscilla- tor circuit which may be driven either by using an exter- nal crystal as a time base or from a TTL–compatible clock signal. The oscillator circuitry provides the internal clocking signals to the on–chip CPU and I/O circuitry.
Page 125 INSTRUCTION TIMING The internal clocking signals are divided to produce the necessary clock phases, state times, and machine cycles which define the sequential execution of instruc- tions. Two clock oscillator periods define one state time. The first clock oscillator pulse period of a state time is called the Phase 1 clock.
Page 126 USER’S GUIDE BYTE–WIDE RAM INSTRUCTION EXECUTION TIMING Figure 15–3 P1 P2 P1 P2 P1 P2 XTAL2 OPCODE NEXT OPCODE FETCH FETCH (DISCARD) A) 1–BYTE, 1–CYCLE INSTRUCTION (E.G., DEC A) OPCODE READ 2ND FETCH BYTE (OPERAND) B) 2–BYTE, 1–CYCLE INSTRUCTION (E.G., MOV A, #DATA) OPCODE FETCH C) 1–BYTE, 2–CYCLE INSTRUCTION (E.G., INC DPTR)
Page 127 Multiplexed address and data information appear on the Port 0 pins as Program Memory fetches are performed on the Expanded Bus. The falling edge of ALE can be used to signal when the lowest eight bits of valid ad- dress information are being output on Port 0 when such a fetch occurs.
Page 128 USER’S GUIDE EXPANDED DATA MEMORY READ Figure 15–5 MACHINE CYCLE PSEN DATA SAMPLED PORT 0 PORT 2 PCH/P2 * PCL OUT if program memory also on Expanded Bus – float if not. **PCH OUT if program memory also on Expanded Bus. EXPANDED DATA MEMORY WRITE Figure 15–6 MACHINE CYCLE PSEN...
Page 129 EXPANDED DATA MEMORY TIMING The timing for the Expanded Data Memory access cycle is illustrated in Figures 15–5 and 6. Accesses to Data Memory on the Expanded Bus will occur any time that a MOVX instruction is executed that references a Data Memory location that is mapped outside the area which has been assigned to the Expanded Bus via the Parti- tion and Range.
Page 130: Section 16 Program Loading
USER’S GUIDE SECTION 16: PROGRAM LOADING INTRODUCTION Program loading is performed to initialize the contents of NV RAM and to configure the microcontroller. Load- ing is done using a Bootstrap ROM Loader built into all members of the Secure Microcontroller family. When this Bootstrap Loader is invoked, the user’s NV RAM appears as data memory to the ROM and can therefore be initialized.
Page 131 The indeterminate area contains various stacks and buffers used by the loader, and a given byte in this area may or may not be modified by the loader. As such the user should not rely on the bootstrap loader preserving any data in this area.
Page 132 USER’S GUIDE INVOKING AND EXITING THE LOADER ON THE DS5001/DS5002 SERIES Figure 16–1 Power Up Reset PROG=0 CRC=1 ROM code calculates CRC of program space CRC Fails MODEM=1 ROM code initializes modem to allow for call for help 050396 131/173 PROG=0 CRC=1 AUTOBAUD Routine:...
Page 133 SERIAL PROGRAM LOAD MODE The Serial Bootstrap Loader provides the easiest meth- od of initially loading application software into the non- volatile RAM. Communication can be performed over a standard asynchronous serial communications port us- ing a terminal emulator program with 8–N–1 (8 data bits, no parity, 1 stop bit) protocol settings.
Page 134 USER’S GUIDE AUTO–BAUD RATE DETECTION The Serial Bootstrap Loader has the capability of deter- mining which of the six supported baud rate frequencies is being used for communication and initializing its inter- nal hardware for communication at that frequency. When the Program Load mode is first invoked, the de- vice will watch for activity on the serial port.
Page 135 BOOTSTRAP LOADER INITIALIZATION When loader mode is invoked, the device will await an incoming <CR> character at a valid baud rate through either the serial port (in Serial Program Load mode) or via the parallel interface (in Parallel Program Load mode).
Page 136 USER’S GUIDE An address will always be the right–most four digits of a hexadecimal number. For example, the following hexa- decimal numbers will result in the following addresses: 000AH 00ABH 0ABCH ABCD 0ABCDH ABCDE 0BCDEH The D and F commands allow optional addresses to be entered.
Page 137 F byte [begin–address [end–address]] Fill memory with the value of the specified byte. An op- tional address range may be specified. Data is read from ports 0, 1, 2 and 3 and is printed as four pairs of hexadecimal digits. A CRC–16 is computed from 0 to CRC_RANGE minus 2 and the computed CRC is put into CRC_RANGE minus one and CRC_RANGE.
Page 138 USER’S GUIDE unaffected by this command. DS5001/DS5002: W [CRC/MCON/MSL/RPCTL] byte Writes byte to the requested register. The SL bit is unaf- fected by this command. This command is discussed in greater detail later in this section. Set the Security Lock. Only the U and Z commands may be given after the Security Lock is set.
Page 139 compared to the computed value for the record, and if different, the error message E:BADCKS is printed out. Unfortunately, the data bytes for this record will have been put to memory already. End of Data records (01) do not check for valid checksums. After a byte is put to memory, it is read back immediately to see if it is the same.
Page 140 USER’S GUIDE INTEL HEX FILE FORMAT 8051–compatible assemblers produce an absolute out- put file in Intel Hex format. These files are composed of a series of records. Records in an Intel Hex file have the following format: <Header><Hex Information><Record Terminator> The specific record elements are detailed as follows: : II aaaa tt dddddd ...
Page 141 PARALLEL PROGRAM LOAD OPERATION The DS5000 Parallel Program Load mode is compatible with the Program mode of the 87C51. The hardware configuration used for this mode of operation is shown in PARALLEL PROGRAM LOAD CONFIGURATION Figure 16–3 PROGRAM ADDRESS PROGRAM CONTROL PARALLEL PROGRAM LOAD CYCLES Figure 16–4 P2.3–P2.0...
Page 142 USER’S GUIDE PARALLEL PROGRAM LOAD MODE Table 16–3 summarizes the selection of the available Parallel Program Load cycles. Figure 16–4 illustrates the timing associated with these cycles. 8751–COMPATIBLE PROGRAM LOAD CYCLES Table 16–3 MODE Program Security Set Verify Prog Expanded Verify Expanded Prog MCON or Key Verify MCON...
Page 143 PARALLEL PROGRAMMING CONCERNS Dallas Semiconductor highly recommends using the serial load mode for programming the DS5000. It has proven highly reliable and easy to use. In the event that parallel programming is still desirable to some users, several incompatibilities have been discovered in con- ventional device programmers.
Page 144: Section 17 Real-Time Clock
USER’S GUIDE SECTION 17: REAL–TIME CLOCK Many user applications require a time–of–day clock. For this reason, all Secure Microcontroller modules have real–time clock (RTC) options. These include the DS5000T DIP and the DS2250T, DS2251T, and DS2252T SIMMs. In addition, users of the monolithic microprocessor chips will frequently connect to a Dallas Semiconductor RTC.
Page 145 The timekeeper contains a shift register with 128 loca- tions. The first 64 locations correspond to a pattern shown in Figure 17–2. The next 64 are time data. Be- fore access to time data may occur, the 64–bit pattern must be written. The incoming bits are checked by a pattern recognition circuit.
Page 146 USER’S GUIDE PATTERN COMPARISON REGISTER DESCRIPTION Figure 17–2 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 050396 145/173 CODE...
Page 147 DS1215 REGISTER ENTRY FLOWCHART Figure 17–3 Set ECE2 bit in the MCON register to a logic 1 Perform a dummy read operation to reset clock pattern recognition circuit* To open clock, write the 64–bit serial pattern by using A2 and A0 embedded address lines Are clock time registers to be...
Page 148 USER’S GUIDE DS1215 TIME REGISTERS DESCRIPTION Figure 17–4 CLOCK REGISTER # 12/24 REGISTERS The time information is contained in eight registers that are each 8 bits long. After the 64–bit recognition pattern has been received, data in these registers is accessed one bit at a time which is shown conceptually in Figure 17–4.
Page 149 TIME REGISTER EXAMPLES Figure 17–5 CLOCK REGISTER # The time indicated is 11 o’clock PM, 12 minutes, 51.89 seconds. The date indicated is Sunday, October 30th, 1988. The time indicated is 2300 hour, 59 minutes, 51.89 seconds. The date indicated is Monday, November 22nd, 1988. USER’S GUIDE RANGE (BCD) 050396 148/173...
Page 150 USER’S GUIDE DS1283 WATCHDOG TIMEKEEPER CHIP The DS2251T and DS2252T use the DS1283 Byte– wide RTC. This is also the clock of choice for users designing with the microprocessor chips (DS5000FP, DS5001FP, and DS5002FP). This clock gives perma- nently powered time–of–day monitoring. The clock runs from an internal 32 KHz crystal (in the modules) and is generally independent of the microcontroller.
Page 151 DS2251T/DS2252T RTC BLOCK DIAGRAM Figure 17–6 DS2251T DS2252T P3.2 (INT0) MEMORY MAP In both the DS2251T and DS2252T, the RTC function is memory mapped. It is accessed using the peripheral selects. First, the PES bit at MCON.2 must be set to a logic 1.
Page 152 USER’S GUIDE DS1283 REAL–TIME CLOCK MEMORY MAP Figure 17–7 CLOCK, CALENDAR, TIME–OF–DAY ALARM REGISTERS COMMAND REGISTERS (RETRIGGERABLE/ WATCHDOG REPETITIVE ALARM COUNTDOWN REGISTERS ALARM) USERS REGISTERS 050396 151/173 BIT 7 ADDRESS 0.1 SECONDS 10 SECONDS 10 MINUTES 10 MIN ALARM 12–24 12–24 10 DATE EOSC...
Page 153 The time, calendar, and alarms are controlled by the information in these 14 registers. In particular, the Com- mand register controls most functions. This is described in Figure 17–8. There are two additional bits that deserve mention. These reside in the register at address 09h.
Page 154 USER’S GUIDE DS1283 RTC INTERRUPTS The DS1283 provides two interrupt functions. They are time–of–day alarm and a watchdog alarm. The watch- dog alarm is a user programmed periodic interval time– out. It is programmed using registers 0Ch and 0Dh. The time–of–day alarm is controlled by the registers at loca- tions 03h, 05h, and 07h as well as the command regis- ALARM MASKBIT OPERATION Figure 17–9...
Page 155 APPLICATION: USING THE DS5000T RTC (DS1215 EXAMPLE) The DS5000T and DS2250T use the DS1215 Phantom Time Chip RTC. This clock is basically a serial device that uses a single address bit as an input and a single data bus bit as an output. The following program is an example of how to use this clock.
Page 156 USER’S GUIDE lcall CLOSE TMOD, #20H TH1, #0FAH TL1, #0FAH PCON, #80H SCON, #52H TCON, #40H SBUF cjne A, #’R, H lcall OPEN lcall RBYTE SBUF, djnz sjmp cjne A, #’W’, J lcall OPEN SBUF lcall WBYTE djnz sjmp SBUF, sjmp ;...
Page 157 OPEN: LCALL OPENA: LCALL LCALL SWAP DJNZ ;******************************** ;*** SUBROUTINE TO CLOSE THE RTC ;******************************** ; This subroutine insures that the registers of the timekeeper ; are closed by executing 9 successive reads of the date and time ; registers. The subroutine returns with both the accumulator ;...
Page 158 USER’S GUIDE ;************************************ ;*** SUBROUTINE TO WRITE A DATA BYTE ;************************************ ; This subroutine performs a “context switch” to the CE2 data ; space and then writes one byte from the accumulator to the ; timekeeping device. Then it switches back to the CE1 data ;...
Page 159 APPLICATION: USING THE DS2251T RTC (DS1283 EXAMPLE) The DS2251T or DS2252T use the DS1283 Byte–wide type real–time clock (RTC). This clock is accessed in a parallel fashion like a RAM. The user simply writes to the registers to set the time and control functions. The fol- lowing program is an example of how to use this clock.
Page 160 USER’S GUIDE ;Set Time LCALL WBYTE DPTR, LCALL TEXT_OUT LCALL HEX_IN LCALL WBYTE DPTR, LCALL TEXT_OUT LCALL HEX_IN LCALL WBYTE DPTR, LCALL TEXT_OUT LCALL HEX_IN LCALL WBYTE DPTR, LCALL TEXT_OUT LCALL HEX_IN LCALL WBYTE DPTR, LCALL TEXT_OUT LCALL HEX_IN LCALL WBYTE DPTR, LCALL...
Page 161 LCALL RBYTE LCALL HEX_OUT LCALL CHAR_OUT LCALL RBYTE LCALL HEX_OUT DPTR, LCALL TEXT_OUT LCALL RBYTE LCALL HEX_OUT LCALL CHAR_OUT LCALL RBYTE LCALL HEX_OUT LCALL CHAR_OUT LCALL RBYTE LCALL HEX_OUT LCALL CHAR_OUT LCALL RBYTE LCALL HEX_OUT DPTR, LCALL TEXT_OUT LCALL WBYTE SJMP CONTINUE ;Utilities...
Page 162 USER’S GUIDE SJMP HEX_LP HEX_OUT: OUT_LP: SWAP PUSH CJNE HEX_OK HEX_OK: LCALL CHAR_OUT DJNZ TEXT_OUT: PUSH WT1: MOVC DPTR LCALL CHAR_OUT SJMP WT2: CHAR_IN: CHAR_OUT: SBUF, RBYTE: PUSH MCON MCON, MOVX MCON WBYTE: PUSH MCON MCON, MOVX @R0, 050396 161/173 #0FH #10, #30H...
Page 163 MCON YEAR: CR,LF,’YEAR (0 – 99) MONTH: CR,LF,’MONTH (1 – 12) : DAY: CR,LF,’DAY OF MONTH DAYW: CR,LF,’DAY OF WEEK HOUR: CR,LF,’HOUR (0 – 23) MINUTE: CR,LF,’MINUTE (0 – 59): TRIGGER: CR,LF,’PRESS ANY KEY TO SET THIS TIME’,CR,LF,0 TEXT0: CR,LF,’****** DALLAS SEMICONDUCTOR *******’ CR,LF,’DS1283 SAMPLE DEMONSTRATION PROGRAM’,CR,LF CR,LF,’DO YOU WANT TO SET THE TIME (Y/N) ? ’,0 TEXT1:...
Page 164: Section 18 Troubleshooting
USER’S GUIDE SECTION 18: TROUBLESHOOTING Dallas Semiconductor’s Secure Microcontroller family has proven itself to be a reliable and easy–to–use prod- uct. As with any highly–integrated device, however, questions and or problems can arise during its use and development. Many of these stem from inadvertent at- tempts to design with the Secure Microcontroller as though it were exactly an 8051.
Page 165 lithium batteries have a very long time constant. Putting the device on the shelf for one to two weeks may restore enough voltage to battery back the memory again. The lifetime of such a battery will be reduced, however. UNABLE TO INVOKE STOP MODE Unlike the 8051, the STOP bit in the PCON register is Timed Access protected.
Page 166 USER’S GUIDE HIGH CURRENT DRAIN IN STOP MODE Secure Microcontrollers draw approximately 80 A of in Stop mode. However, the EA pin has a resistive load of between 40K to 125K ohms. If EA is connected to +5V, this pin will draw between 40 A to 125 A. This current can be eliminated by grounding the EA pin and locking the device via the bootstrap loader.
Page 167 Battery backed signals Do not connect lithium backed chip enables or signals to non–backed devices. This produces a drain on the lith- ium cell. On the DS5001 and DS5002, PE1 and PE2 as a well as CE1 – 4 are lithium backed. PE3 and PE4 are not backed and can be connected to normal circuits.
Page 168: Section 19 Instruction Set Details
USER’S GUIDE SECTION 19: INSTRUCTION SET DETAILS INSTRUCTION CODE MNEMONIC MNEMONIC ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDCA,direct ADDC A, @Ri ADDC A,#data SUBB A, Rn SUBB A,direct SUBB A, @Ri SUBB A,#data INC A INC Rn...
Page 169 INSTRUCTION CODE MNEMONIC MNEMONIC DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL di- rect,#data XRL A, Rn XRL A, direct...
Page 170 USER’S GUIDE INSTRUCTION CODE MNEMONIC MNEMONIC RL A RLC A RR A RRC A SWAP A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, MOV direct1, direct2...
Page 171 INSTRUCTION CODE MNEMONIC MNEMONIC MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A + DPTR MOVC A, @A + PC MOVX A, @Ri MOVX @DPTR MOVX @Ri, A MOVX @DPTR,A PUSH direct POP direct XCH A, Rn XCH A, direct...
Page 172 USER’S GUIDE INSTRUCTION CODE MNEMONIC MNEMONIC CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, bit ORL C, bit ORL C, bit MOV C, bit MOV bit, C 050396 171/173 BYTE BYTE CYCLE CYCLE EXPLANATION...
Page 173 INSTRUCTION CODE MNEMONIC MNEMONIC ACALL addr 11 LCALL addr 16 RETI AJMP addr 11 LJMP addr 16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JC rel JNC rel JB bit, rel Byte 1 Byte 2 Byte 2 Byte 3 Byte 1...
Page 174 USER’S GUIDE INSTRUCTION CODE MNEMONIC MNEMONIC JNB bit, rel JBC bit, direct CJNE A, direct CJNE A, #data CJNE Rn, #data rel CJNE @Ri, #data rel DJNZ Rn, rel DJNZ direct rel 050396 173/173 BYTE BYTE CYCLE CYCLE EXPLANATION EXPLANATION (PC) = (PC) + 3 IF (bit) = 0 THEN Byte 2...

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