AOpen MX3L User Manual page 54

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Chipset Features
Auto Configuration
Enabled
Disabled
Chipset Features
DRAM Speed
Selection
50 ns
60 ns
Chipset Features
MA Wait State
Slow
Fast
Chipset Features
EDO RAS# to CAS#
Delay
2
3
Chipset Features
EDO RAS#
Precharge Time
3
4
Auto Configuration
When Enabled, the DRAM and cache related timing
are set to pre-defined value according to CPU type
and clock. Select Disable if you want to specify your
own DRAM timing.
DRAM Speed Selection
There are two sets of DRAM timing parameters can
be automatically set by BIOS, 50ns and 60ns.
MA Wait State
To enable or disable one additional MA (DRAM
memory address) wait state. The default setting is
Slow. Set it to Fast if you have heavy loading (many
chip count) or lower speed DRAM.
EDO RAS# to CAS# Delay
This option allows you to set the wait state between
row address strobe (RAS) and column address
strobe (CAS) signals.
EDO RAS# Precharge Time
This parameter specifies the number of clocks
required to deassert the RAS signal to prevent DRAM
from losing data after performing a read. This
operation is called Precharge.
AWARD BIOS
3-11

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