Chipset - Asus Barebone System T2-PH2 User Manual

5.4.5

Chipset

The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD
Graphic Adapter Priority
Internal Graphics Mode Select
Graphic Memory Type
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters throug the DRAM sub-items. The
following sub-items appear when this item is disabled.
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available. Configuration options: [6 Clocks]
[5 Clocks] [4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks] [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2 Clocks] [3 Clocks]
[4 Clocks] [5 Clocks] [6 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Configuration options: [4 Clock] [5 Clock] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clock]
Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks]
[6 Clocks]
5-24
[Enabled]
[PCI Express/Int-VGA]
[Enabled, 8MB]
[Auto]
Enable or disable
Configure DRAM Timing
by SPD.
Chapter 5: BIOS setup