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MB90420/5 (A) Series
Fujitsu MB90420/5 (A) Series Manuals
Manuals and User Guides for Fujitsu MB90420/5 (A) Series. We have
1
Fujitsu MB90420/5 (A) Series manual available for free PDF download: Hardware Manual
Fujitsu MB90420/5 (A) Series Hardware Manual (551 pages)
F2MC-16LX FAMILY 16-BIT MICROCONTROLLERS
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 4.74 MB
Table of Contents
Table of Contents
4
Chapter 1 General
25
Overview of Product
25
Table 1-1 Overview of MB90420/5 (A) Series
25
Features
26
Table 1-2 Features of MB90420/5 (A) Series
26
Block Diagram
28
Fig. 1.1 Block Diagram
28
Package Dimension
29
Fig. 1.3 Package Dimension (LQFP100)
30
Pin Assignment
31
Fig. 1.4 Pin Assignment (QFP100)
31
Fig. 1.5 Pin Assignment (LQFP100)
32
Pin Description
33
Table 1-3 Pin Description
33
I/O Circuits
36
Table 1-4 I/O Circuits
36
Notes on Handling Devices
38
Fig. 1.6 Example of Using External Clock
39
Fig. 1.7 Power Input Pins
39
CC /Vss )
39
Fig. 1.8 Undefined-Value Output Timing Chart
40
Chapter 2 CPU
41
Cpu
43
Memory Space
44
Memory Map
46
Fig. 2.2 Memory Map
46
Addressing
47
Fig. 2.3 Memory Management in Linear and Bank Types
47
Linear Type Addressing
48
Fig. 2.5 Example of 32-Bit Ggeneral-Purpose Register Indirect Specification in Linear Type
48
Bank Type Addressing
49
Table 2-1 Access Space for each Bank Register and Major Use of Access Space
49
Fig. 2.6 Example of Bank Type Addressing
50
Table 2-2 Addressing and Default Spaces
50
Allocation of Multi-Byte Length Data on Memory
51
Fig. 2.7 Storage of Multi-Byte Data in RAM
51
Fig. 2.8 Storage of Multi-Byte Operand
51
Fig. 2.9 Storage of Multi-Byte Length Data in Stack
52
Fig. 2.10 Access to Multi-Byte Length Data on Bank Boundary
52
Register
53
Fig. 2.11 Dedicated and General-Purpose Registers
53
Dedicated Registers
54
Fig. 2.12 Configuration of Dedicated Registers
54
Table 2-3 Initial Values of Dedicated Registers
55
Accumulator (A)
56
Fig. 2.13 Data Transfer to Accumulator
56
Fig. 2.14 Example of Transfer between al and AH of Accumulator (A) (8-Bit Immediate Value, Zero-Extended)
57
Fig. 2.15 Example of Transfer between al and AH of Accumulator (A) (8-Bit Immediate Value, Sign-Extended)
57
Fig. 2.16 Example of 32-Bit Data Transfer to Accumulator (A) (Register Indirect)
58
Fig. 2.17 Example of Transfer between al and AH of Accumulator (A) (16-Bit, Register Indirect)
58
Stack Pointer (USP, SSP)
59
Table 2-4 Stack Address Specification
59
Fig. 2.18 Stack Operation Instructions and Stack Pointers
60
Processor Status (PS)
61
Fig. 2.19 Configuration of Processor Status (PS)
61
Condition Code Register (PS: CCR)
62
Fig. 2.20 Configuration of Condition Code Register (CCR)
62
Register Bank Pointer (PS: RP)
63
Fig. 2.21 Configuration of Register Bank Pointer (RP)
63
Fig. 2.22 Physical Address Conversion Rules in General-Purpose Register Area
63
Interrupt Level Mask Register (PS: ILM)
64
Fig. 2.23 Configuration of Interrupt Level Mask Register (ILM)
64
Table 2-5 Interrupt Level Mask Register (ILM) and Interrupt Level (High/Low)
64
Program Counter (PC)
65
Fig. 2.24 Program Counter (PC)
65
Direct Page Register (DPR)
66
Fig. 2.26 Direct Page Register (DPR) Setting and Data Access Example
66
Bank Register (PCB, DTB, USB, SSB, and ADB)
67
General-Purpose Register
68
Fig. 2.27 Allocation and Configuration of General-Purpose Register Banks in Memory Space
68
Table 2-6 Typical Function of the General-Purpose Register
69
Prefix Codes
70
Bank Select Prefix (PCB, DTB, ADB, and SPB)
71
Table 2-7 Bank Select Prefix
71
Table 2-8 Instructions Unaffected by Bank Select Prefix
71
Common Register Bank Prefix (CMR)
72
Table 2-9 Instructions Requiring Care When Using Bank Select Prefix
72
Table 2-10 Instructions Requiring Care When Using Bank Select Prefix (CMR)
72
Flag Change Inhibit Prefix (NCC)
73
Table 2-11 Instructions Requiring Care When Using Flag Change Inhibit Prefix (NCC)
73
Restrictions on Prefix Code
74
Fig. 2.28 Interrupt/Hold Inhibition
74
Table 2-12 Prefix Code and Interrupt/Hold Inhibit Instruction
74
Fig. 2.29 Interrupt/Hold Inhibition Instruction and Prefix Code
75
Fig. 2.30 Successive Prefix Codes
75
Chapter 3 Reset
77
Overview of Reset
79
Table 3-1 Reset Factor
79
Reset Factors and Oscillation Stabilization Wait Time
81
Fig. 3.1 Oscillation Stabilization Wait Time of Evaluation Products/Flash and Mask Products at Power-On Reset
81
Mask Products at Power-On Reset
81
Table 3-2 Reset Factors and Oscillation Stabilization Wait Times
81
Table 3-3 Oscillation Stabilization Wait Time Based on Setting of Clock Selection Register (CKSCR)
82
External Reset Pin
83
Reset Operation
84
Fig. 3.5 Reset Operation Flow
84
Fig. 3.6 Transfer of Reset Vectors and Mode Data
85
Reset Factor Bit
86
Fig. 3.7 Block Diagram of Reset Factor Bit
86
Fig. 3.8 Configuration of Reset Factor Bit (Watchdog Timer Control Register)
87
Table 3-4 Correspondence of Reset Factor Bit Value and Reset Factor
87
State of each Pin at Reset
88
Chapter 4 Clock
89
Overview of Clock
91
Fig. 4.1 Clock Supply Map
92
Block Diagram of Clock Generation Section
93
Fig. 4.2 Block Diagram of Clock Generation Section
93
Clock Select Register (CKSCR)
95
Fig. 4.3 Configuration of Clock Select Register (CKSCR)
95
Table 4-1 Function of each Bit of Clock Select Register (CKSCR)
96
Clock Mode
97
Fig. 4.3 Transition Diagram of Machine Clock Selection State
99
Oscillation Stabilization Wait Time
100
Fig. 4.5 Operation Immediately after Oscillation Started
100
Connection of Oscillator and External Clock
101
Fig. 4.6 Connection of Crystal or Ceramic Oscillator
101
Fig. 4.7 Connection of External Clock
101
Chapter 5 Low-Power Consumption Mode
103
Overview of Low-Power Consumption Mode
105
Fig. 5.1 CPU Operating Mode and Current Consumption
105
Block Diagram of Low-Power Consumption Controller
107
Fig. 5.2 Block Diagram of Low-Power Consumption Controller
107
Low-Power Consumption Mode Control Register (LPMCR)
109
Fig. 5.3 Configuration of Low-Power Consumption Mode Control Register (LPMCR)
109
Table 5-1 Function of each Bit of Low-Power Consumption Mode Control Register (LPMCR)
110
Table 5-2 Instructions at Transition to Low-Power Consumption Mode
111
CPU Intermittent Operation Mode
112
Fig. 5.4 Clock in CPU Intermittent Operation Mode
112
Standby Mode
113
Table 5-3 Operating State in Standby Mode
113
Sleep Mode
114
Fig. 5.5 Cancellation of Sleep Mode by Interrupt
115
Time-Base Timer Mode
116
Timer Mode
117
Fig. 5.6 Cancellation of Timer Mode (External Reset)
118
Stop Mode
119
Fig. 5.7 Cancellation of Stop Mode (External Reset)
120
State Transition Diagram
121
Fig. 5.8 State Transition Diagram
121
Table 5-4 Operation State in Low-Power Consumption Mode
122
Pin State in Standby Mode, at Reset
123
Table 5-5 each Pin State in Single Chip Mode
123
Precautions at Using Low-Power Consumption Mode
124
Chapter 6 Interrupt
127
Overview of Interrupt
129
Fig. 6.1 General Flow of Interrupt Operation
130
Interrupt Factor and Interrupt Vector
131
Table 6-1 Interrupt Vectors
131
Interrupt Control Registers and Resources
133
Table 6-3 Interrupt Control Register List
133
Interrupt Control Register (ICR00 to ICR15)
134
Fig. 6.2 Interrupt Control Register (ICR00 to ICR15) at Writing
134
Fig. 6.3 Interrupt Control Register (ICR00 to ICR15) at Reading
135
Fig. 6.4 Configuration of Interrupt Control Register (ICR)
136
Function of Interrupt Control Register
137
Table 6-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels
137
Hardware Interrupt
139
Table 6-7 Mechanism Related to Hardware Interrupt
139
Fig. 6.5 Hardware Interrupt Request During Writing to the Resource Control Register Area
140
Table 6-8 Hardware Interrupt Inhibit Instructions
140
Operation of Hardware Interrupt
142
Fig. 6.6 Operation of Hardware Interrupt
142
Processing at Interrupt Operation
143
Fig. 6.7 Flow of Handling Processing
143
Use Procedure for Hardware Interrupt
144
Fig. 6.8 Use Procedure for Hardware Interrupt
144
Multiple Interrupts
145
Fig. 6.9 Example of Multiple Interrupts
145
Hardware Interrupt Handling Time
146
Fig. 6.10 Interrupt Processing Time
146
Table 6-9 Compensation Value (Z) of Interrupt Handling Time
146
Software Interrupt
147
Fig. 6.11 Operation of Software Interrupt
148
EI os Interrupt
149
EI 2 os Descriptor (ISD)
149
EI os Descriptor (ISD)
151
Table 6-10 Correspondence between Channel Number and Descriptor Address
151
Each Register of EI os Descriptor (ISD)
152
Fig. 6.14 Configuration of Data Counter (DCT)
152
Fig. 6.15 Configuration of I/O Register Address Pointer (IOA)
152
Fig. 6.17 Configuration of Buffer Address Pointer (BAP)
154
EI os Operation
155
Use Procedure for EI os
156
EI os Handling Time
157
Table 6-13 Compensation Value (Z) for Interrupt Handling Time
158
Exception Handling Interrupt
159
Stack Operation for Interrupt Handling
160
Fig. 6.20 Stack Operation at Starting Interrupt Handling
160
Fig. 6.21 Stack Area
161
Program Example for Interrupt Handling
162
Chapter 7 Mode Setting
165
Mode Setting
167
Fig. 7.1 Classification of Mode
167
Mode Pins (MD2 to MD0)
168
Table 7-1 Setting of Mode Pins
168
Mode Data
169
Fig. 7.2 Configuration of Mode Data
169
Table 7-2 Bus Mode Setting Bits and Functions
169
Fig. 7.3 Relationship between Access Areas and Physical Addresses in Single-Chip Mode
170
Table 7-3 Relationships between Mode Pins and Mode Data
170
Chapter 8 I/O Port
171
Overview of I/O Port
173
Table 8-1 List of each Port Functions
174
Registers and Assignment of Pins Serving as External Pins
175
Table 8-2 Registers for each Port
175
Port 0
176
Fig. 8.1 Block Diagram of Pins of Port 0
177
Registers for Port 0 (PDR0, DDR0)
178
Operation of Port 0
179
Table 8-6 State of Port 0 Pins
180
Port 1
181
Table 8-7 Pins of Port 1
181
Fig. 8.2 Block Diagram of Pins of Port 1
182
Registers for Port 1 (PDR1, DDR1)
183
Operation of Port 1
184
Table 8-10 State of Port 1 Pins
185
Port 3
186
Table 8-11 Pins of Port 3
186
Fig. 8.3 Block Diagram of Pins of Port 3
187
Registers for Port 3 (PDR3, DDR3)
188
Operation of Port 3
189
Table 8-14 State of Port 3 Pins
190
Port 4
191
Table 8-15 Pins of Port 4
191
Fig. 8.4 Block Diagram of Pins of Port 4
192
Registers for Port 4 (PDR4, DDR4)
193
Operation of Port 4
194
Table 8-18 State of Port 4 Pins
195
Port 5
196
Table 8-19 Pins of Port 5
196
Fig. 8.5 Block Diagram of Pins of Port 5
197
Registers for Port 5 (PDR5, DDR5)
198
Operation of Port 5
199
Table 8-22 State of Port 5 Pins
200
Port 6
201
Table 8-23 Pins of Port 6
201
Fig. 8.6 Block Diagram of Pins of Port 6
202
Registers for Port 6 (PDR6, DDR6)
203
Operation of Port 6
204
Table 8-26 State of Port 6 Pins
205
Port 7
206
Fig. 8.7 Block Diagram of Pins of Port 7
207
Registers for Port 7 (PDR7, DDR7)
208
Operation of Port 7
209
Table 8-30 State of Port 7 Pins
210
Port 8
211
Fig. 8.8 Block Diagram of Pins of Port 8
212
Registers for Port 8 (PDR8, DDR8)
213
Operation of Port 8
214
Table 8-34 State of Port 8 Pins
215
Port 9
216
Table 8-35 Pins of Port 9
216
Fig. 8.9 Block Diagram of Pins of Port 9
217
Registers for Port 9 (PDR9, DDR9)
218
Operation of Port 9
219
Table 8-38 State of Port 9 Pins
220
Program Example Using I/O Ports
221
Fig. 8.10 Eight-Segment LED Connection Example
221
Chapter 9 Watchdog Timer/Time-Base Timer/Watch Timer (Sub-Clock)
225
Overview of Watchdog Timer, Time-Base Timer, and Watch Timer
225
Block Diagram of Watchdog Timer, Time-Base Timer, and Watch Timer
226
Fig. 9.1 Block Diagram of Watchdog Timer, Time-Base Timer, and Watch Timer
226
List of Watchdog Timer, Time-Base Timer, and Watch Timer Registers
227
Watchdog Timer Control Register (WDTC)
228
Fig. 9.2 Watchdog Timer Control Register (WDTC)
228
Table 9-1 PONR, STBR, WRST, ERST, SRST (Reset Factor Bits)
228
Table 9-2 WT1 and 0 (Interval Time Select Bits)
229
Time-Base Timer Control Register (TBTC)
230
Fig. 9.3 Time-Base Timer Control Register (TBTC)
230
Watch Timer Control Register (WTC)
231
Fig. 9.4 Watch Timer Control Register
231
Table 9-4 Selection of Watch Timer Interval
232
Operation of Watchdog Timer, Time-Base Timer, and Watch Timer
233
Operation of Watchdog Timer
234
Fig. 9.5 Watchdog Timer Operation
234
Fig. 9.6 Clearing Timing and Watchdog Timer Interval Time
235
Operation of Time-Base Timer
236
Table 9-6 Time-Base Timer Counter Clear and Oscillation Stabilization Wait Time
237
Operation of Watch Timer
238
Precautions at Using Watchdog Timer and Time-Base Timer
239
Fig. 9.7 Operation of Time-Base Timer
240
Program Examples of Watchdog Timer and Time-Base Timer
241
Chapter 10 16-Bit Reload Timer
243
Overview of 16-Bit Reload Timer
245
Table 10-2 Interval Time of 16-Bit Reload Timer
246
Configuration of 16-Bit Reload Timer
247
Fig. 10.1 Block Diagram of 16-Bit Reload Timer
247
Pins of 16-Bit Reload Timer
249
Fig. 10.2 Block Diagram of Pins of 16-Bit Reload Timer
249
Table 10-4 Pins of 16-Bit Reload Timer
249
Registers for 16-Bit Reload Timer
250
Fig. 10.3 Registers for 16-Bit Reload Timer
250
Timer Control Status Register (Upper) (TMCSR0/1H)
251
Table 10-5 Function of each Bit of Timer Control Status Register (Upper) (TMCSR0, TMCSR1: H)
252
Timer Control Status Register (Lower) (TMCSR0/1L)
253
Fig. 10.5 Timer Control Status Register (Lower) (TMCSR0/1L)
253
Table 10-6 Function of each Bit of Timer Control Status Register (Lower) (TMCSR0/1L)
254
16-Bit Timer Register (TMR0/1)
255
Fig. 10.6 16-Bit Timer Register (TMR0/1)
255
16-Bit Reload Register (TMRLR0/1L, TMRLR0/1H)
256
Fig. 10.7 16-Bit Reload Register (TMRLR0/1L, TMRLR0/1H)
256
Interrupt of 16-Bit Reload Timer
257
Table 10-7 Interrupt Control Bits and Interrupt Factors of 16-Bit Reload Timer
257
Operation of 16-Bit Reload Timer
258
Fig. 10.8 Setting of Internal Clock Mode
258
Fig. 10.9 Setting of Event Counter Mode
258
Fig. 10.10 State Transition Diagram of Counter
259
Internal Clock Mode (Reload Mode)
260
Fig. 10.11 Count Operation in Reload Mode (Operation of Software Trigger)
260
Fig. 10.12 Count Operation in Reload Mode (Operation of External Trigger)
261
Fig. 10.13 Count Operation in Reload Mode (Operation of Software Trigger and Gate Input)
261
Internal Clock Mode (One-Shot Mode)
262
Fig. 10.14 Count Operation in One-Shot Mode (Operation of Software Trigger)
262
Fig. 10.15 Count Operation in One-Shot Mode (Operation of External Trigger)
263
Fig. 10.16 Count Operation in One-Shot Mode (Operation of Software Gate Input)
263
Event Count Mode
264
Fig. 10.17 Count Operation in Reload Mode (Operation of Event Count Mode)
264
Fig. 10.18 Count Operation in One-Shot Mode (Operation of Event Count Mode)
265
Precautions at Using 16-Bit Reload Timer
266
Program Example of 16-Bit Reload Timer
267
Chapter 11 Input Capture
271
Overview of Input Capture
271
Block Diagram of Input Capture
272
Fig. 11.1 Block Diagram
272
List of Input Capture Registers
273
Detailed Explanation of Registers for Input Capture
275
Detailed Explanation of Registers for 16-Bit Free-Run Timer
277
Explanation of Operation
281
16-Bit Input Capture
282
Fig. 11.2 Capture Timing Example for Input Capture
282
Fig. 11.3 Capture Timing for Input Signal
282
16-Bit Free-Run Timer
283
Fig. 11.4 Clearing Counter by Overflow
283
Fig. 11.5 Clearing Counter When Value of 16-Bit Free-Run Timer Matches Value of Compare Clear Register
283
Fig. 11.6 Clearing Timing of 16-Bit Free-Run Timer
284
Fig. 11.7 Count Timing of 16-Bit Free-Run Timer
284
Chapter 12 UART
285
Overview of UART
287
Table 12-1 Function of UART
287
Table 12-2 Operation Mode of UART
288
Configuration of UART
289
Fig. 12.1 Block Diagram of UART
290
Pin of UART
292
Fig. 12.2 Block Diagram of Pins of UART
292
Table 12-4 UART Pins
292
Registers for UART
293
Fig. 12.3 List of UART Registers
293
Control Register (SCR0/1)
294
Fig. 12.4 Control Register (SCR0/1)
294
Table 12-5 Function of each Bit of Control Register (SCR0/1)
295
Mode Register (SMR0/1)
296
Fig. 12.5 Mode Register (SMR0/1)
296
Table 12-6 Function of each Bit of Mode Register (SMR0/1)
297
Status Register (SSR0/1)
298
Fig. 12.6 Status Register (SSR0/1)
298
Table 12-7 Function of each Bit of Status Register (SSR0/1)
299
Input-Data Register (SIDR0/1) and Output-Data Register (SODR0/1)
300
Fig. 12.7 Input Data Register (SIDR0/1)
300
Fig. 12.8 Output Data Register (SODR0/1)
300
Communication Prescaler Control Register (CDCR0/1)
301
Table 12-8 Communication Prescaler
301
Interrupt of UART
302
Table 12-9 UART Interrupt Control Bit and Interrupt Factor
302
Generation of Receive Interrupt and Timing of Flag Set
304
Fig. 12.9 Reception and Timing of Flag Set
304
Generation of Transmit Interrupt and Timing of Flag Set
305
Fig. 12.10 Transmission and Timing of Flag Set
305
Baud Rate of UART
306
Fig. 12.11 UART Baud Rate Selector
307
Baud Rate by Dedicated Baud Rate Generator
308
Table 12-11 Selection of Division Ratio of Machine Clock Prescaler
308
Table 12-12 Selection of Division Ratio to Obtain Synchronous Baud Rate
308
Table 12-13 Selection of Division Ratio to Obtain Asynchronous Baud Rate
309
Baud Rate by Internal Timer (16-Bit Reload Timer)
310
Fig. 12.12 Baud Rate Selector by Internal Timer (16-Bit Reload Timer)
310
Table 12-14 Baud Rate and Reload Value
310
Baud Rate by External Clock
311
Fig. 12.13 Baud Rate Selector by External Clock
311
Operation of UART
312
Table 12-15 Operation Mode of UART
312
Operation in Asynchronous Mode (Operation Mode 0 or 1)
313
Fig. 12.14 Format of Transfer Data (Operation Mode 0 or 1)
313
Fig. 12.15 Transmit Data When Parity Enabled
314
Operation in Synchronous Mode (Operation Mode 2)
315
Fig. 12.16 Format of Transfer Data (Operation Mode 2)
315
Bidirectional Communication Function (Normal Mode)
317
Fig. 12.17 Setting of Operation Mode 0 for UART1
317
Fig. 12.18 Example of Bidirectional Communication Connection for UART1
317
Fig. 12.19 Example of Bidirectional Communication Flow
318
Master/Slave Mode Communication Function (Multiprocessor Mode)
319
Fig. 12.20 Setting of Operation Mode 1 for UART1
319
Fig. 12.21 Example of Master/Slave Mode Communication Connection for UART
319
Table 12-16 Selection of Master/Slave Mode Communication Function
320
Fig. 12.22 Flowchart of Master/Slave Mode Communications
321
Precautions at Using UART
322
Program Example of UART
323
Chapter 13 PPG Timer
325
Overview of PPG Timer
327
Block Diagram of PPG Timer
328
Fig. 13.1 Block Diagram of PPG Timer
328
Registers for PPG Timer
329
List of PPG Timer Registers
329
Detailed Explanation of Registers for PPG Timer
330
Operation of PPG Timer
334
PWM Operation
334
Fig. 13.2 Timing of Disabling PWM Operation Restart
334
Fig. 13.3 Timing of Enabling PWM Operation Restart
334
One-Shot Operation
335
Fig. 13.4 Timing of Disabling One-Shot Operation Restart
335
Fig. 13.5 Timing of Enabling One-Shot Operation Restart
335
Interrupt Factors and Timing
336
Fig. 13.6 Interrupt Output Factors and Timing
336
Chapter 14 LCD Controller/Driver
337
Overview of LCD Controller/Driver
339
Table 14-1 Combination of Bias and Duty
339
Configuration of LCD Controller/Driver
340
Fig. 14.1 Block Diagram for LCD Controller/Driver
340
Internal Split Resistors of LCD Controller/Driver
342
Fig. 14.2 Equivalent Circuit for Internal Split Resistors
342
Fig. 14.3 State When Internal Split Resistors Used
343
Fig. 14.4 Brightness Adjustment When Internal Split Resistors Used
343
External Split Resistors for LCD Controller/Driver
344
Fig. 14.5 External Split Resistor Connection Example
344
Table 14-2 LCD Driving Voltage Setting
344
Fig. 14.6 State When External Split Resistors Used
345
LCD Controller/Driver Pins
346
Fig. 14.7 Block Diagram of Pins Related to LCD Controller/Driver
347
LCD Controller/Driver Registers
348
Fig. 14.8 Registers Related to LCD Controller/Driver
348
LCDC Control Register Lower (LCRL)
349
Fig. 14.9 LCDC Control Register Lower (LCRL)
349
Table 14-3 Function of each Bit of LCDC Control Register Lower (LCRL)
350
LCDC Control Register Higher (LCRH)
351
Fig. 14.10 LCDC Control Register Higher (LCRH)
351
Table 14-4 Function of each Bit of LCDC Control Register Higher (LCRH)
351
LCD Controller/Driver Display RAM
352
Fig. 14.11 Correspondence between Display RAM and Common/Segment Output Pins
352
Table 14-5 Relationship between Common/Segment Output Pins and Display RAM, and Pins also Serving as General-Purpose Ports
354
Table 14-6 Relationship between Duty, Common Output Pins, and Display RAM Bits
354
Explanation of Operation of LCD Controller/Driver
355
Fig. 14.12 Setting of LCD Controller/Driver
355
Output Waveform (1/2 Duty) During Operation of LCD Controller/Driver
356
Table 14-7 Example of Display RAM Data
356
Fig. 14.13 Example of Output Waveform on 1/2 Bias and 1/2 Duty
357
Fig. 14.14 Example of LCD Panel Display Data
358
Output Waveform (1/3 Duty) During Operation of LCD Controller/Driver
359
Table 14-8 Example of Display RAM Data
359
Fig. 14.15 Example of Output Waveform on 1/3 Bias and 1/3 Duty
360
Fig. 14.16 Example of LCD Panel Display Data
361
Output Waveform (1/4 Duty) During Operation of LCD Controller/Driver
362
Fig. 14.17 Example of Output Waveform on 1/3 Bias and 1/4 Duty
363
Fig. 14.18 Example of LCD Panel Display Data
364
Chapter 15 Stepping Motor Controller
366
Fig. 15.1 Block Diagram of Stepping Motor Controller
368
Stepping Motor Controller Registers
369
PWM Control Register
370
PWM1&2 Compare Registers
371
PWM 1&2 Select Registers
372
Explanation of Operation of Stepping Motor Controller
373
Fig. 15.2 Setting Stepping Motor Controller
373
Fig. 15.3 Example of PWM 1, 2 Waveform Output
374
Precautions at Using Stepping Motor Controller
375
Chapter 16 Dtp/External Interrupt Circuit
376
Overview of Dtp/External Interrupt Circuit
378
Table 16-1 Overview of Dtp/External Interrupt
378
Configuration of Dtp/External Interrupt Circuit
380
Fig. 16.1 Block Diagram of Dtp/External Interrupt Circuit
380
Pins of Dtp/External Interrupt Circuit
382
Fig. 16.2 Block Diagram of Dtp/External Interrupt Circuit Pin
382
Table 16-3 Pins of Dtp/External Interrupt Circuit
382
Registers for Dtp/External Interrupt Circuit
383
Dtp/Interrupt Factor Register (EIRR)
383
Fig. 16.3 Registers for Dtp/External Interrupt Circuit
383
Fig. 16.4 Dtp/Interrupt Factor Register (EIRR)
383
Table 16-4 Function of each Bit of Dtp/Interrupt Factor Register (EIRR)
383
Dtp/Interrupt Enable Register (ENIR)
384
Fig. 16.5 Dtp/Interrupt Enable Register (ENIR)
384
Table 16-5 Function of each Bit of Dtp/Interrupt Enable Register (ENIR)
384
Table 16-6 Correspondence between Dtp/Interrupt Control Registers (EIRR and ENIR) and each Channel
384
Request Level Setting Register (ELVR)
385
Fig. 16.6 Request Level Setting Register (ELVR)
385
Table 16-7 Function of each Bit of Request Level Setting Register (ELVR)
385
Table 16-8 Correspondence between Dtp/Interrupt Control Registers (EIRR and ENIR) and each Channel
386
Explanation of Dtp/External Interrupt Circuit Operation
387
Fig. 16.8 Operation of Dtp/External Interrupt Circuit
388
Table 16-9 Control Bits and Interrupt Factors for Dtp/External Interrupt Circuit
388
External Interrupt Function
389
DTP Function
390
Fig. 16.9 Example of Interface with External Peripheral Unit
390
Precautions at Using Dtp/External Interrupt Circuit
391
Fig. 16.10 Clearing Factor Hold Circuit When Level Set
391
Fig. 16.11 Dtp/External Interrupt Factor and Interrupt Request Issued When Interrupt Request Output Enabled
391
Sample Programs for Dtp/External Interrupt Circuit
393
Chapter 17 Delayed Interrupt Generate Module
396
Overview of Delayed Interrupt Generate Module
398
Fig. 17.1 Block Diagram of Delayed Interrupt Generate Module
398
Operation of Delayed Interrupt Generate Module
399
Fig. 17.2 Operation of Delayed Interrupt Generate Module
399
Chapter 18 Timepiece Timer
400
Overview of Timepiece Timer
402
Fig. 18.1 Block Diagram of Timepiece Timer
402
Timepiece Timer Registers
403
Timepiece Timer Control Register
405
Sub-Second Data Register
406
Second/Minute/Hour Data Register
407
Chapter 19 8-/10- Bit A/D Converter
408
Overview of 8-/10-Bit A/D Converter
410
Table 19-1 Conversion Modes of 8-/10-Bit A/D Converter
410
Configuration of 8-/10-Bit A/D Converter
411
Fig. 19.1 Block Diagram of 8-/10-Bit A/D Converter
411
Pins of 8-/10-Bit A/D Converter
413
Table 19-3 Pins of 8-/10-Bit A/D Converter
413
Fig. 19.2 Block Diagram of P60/AN0 to P67/AN7 Pins
414
Registers for 8-/10-Bit A/D Converter
415
Fig. 19.3 Registers for 8-/10-Bit A/D Converter
415
A/D Control Status Register Upper (ADCSH)
416
Fig. 19.4 A/D Control Status Register Higher (ADCSH)
416
Table 19-4 Function of each Bit of A/D Control Status Register Higher (ADCSH)
417
A/D Control Status Register Lower (ADCSL)
418
Fig. 19.5 A/D Control Status Register Lower (ADCSL)
418
Table 19-5 Function of each Bit of A/D Control Status Register Lower (ADCSL)
419
A/D Data Register (ADCRH/ ADCRL)
420
Fig. 19.6 A/D Data Register (ADCRH/ ADCRL)
420
Table 19-6 Function of each Bit of A/D Data Register (ADCR)
421
Interrupt of 8-/10-Bit A/D Converter
422
Table 19-7 Interrupt Control Bits and Interrupt Factors of 8-/10-Bit A/D Converter
422
Explanation of 8-/10-Bit A/D Converter Operation
423
Fig. 19.7 Setting in Single-Shot Conversion Mode
423
Fig. 19.8 Setting in Continuous Conversion Mode
424
Fig. 19.9 Setting in Pause-Conversion Mode
425
Conversion Using EI2OS
426
A/D-Converted Data Protection Function
427
Precautions at Using 8-/10-Bit A/D Converter
429
Sample Program 1 for 8-/10-Bit A/D Converter (EI os Start in Single-Shot Mode)
430
Fig. 19.12 Flow of EI os Start Program (Single-Shot Mode)
430
Sample Program 2 for 8-/10-Bit A/D Converter (EI os Start in Continuous Mode)
432
Fig. 19.13 Flow Chart of EI
432
OS Start Program (Continuous Mode)
432
Sample Program 3 for 8-/10-Bit A/D Converter (EI os Start in Stop Mode)
434
Fig. 19.14 Flow Chart of EI os Start Program (Stop Mode)
434
Chapter 20 Sound Generator
436
Overview of Sound Generator
438
Fig. 20.1 Block Diagram of Sound Generator
438
Sound Generator Registers
439
Sound Control Register
440
Frequency Data Register
442
Fig. 20.2 Relationship between Tone Signal and Register Value
442
Amplitude Data Register
443
Fig. 20.3 Relationship between Register Value and PWM Pulse
443
Decrement Grade Register
444
Tone Count Register
444
Chapter 21 ROM Correction
446
Overview of ROM Correction
448
Fig. 21.1 Block Diagram of ROM Correction
448
Application Example of ROM Correction
451
Fig. 21.2 System Structure Example
451
Correction Example of Program Errors
452
Fig. 21.3 ROM Correction Processing Flow
452
Example of Correction Processing
453
Fig. 21.4 ROM Correction Processing Flow
453
Fig. 21.5 ROM Correction Processing Flow Diagram
454
Chapter 22 ROM Mirror Function Select Module
456
Overview of ROM Mirror Function Select Module
458
Fig. 22.1 Block Diagram of ROM Mirror Function Select Module
458
ROM Mirror Function Select Register (ROMM)
459
Chapter 23 Can Controller
460
Features of CAN Controller
462
Block Diagram of CAN Controller
463
Fig. 23.1 Block Diagram of CAN Controller
463
List of Overall Control Registers
464
Table 23-1 List of Overall Control Registers
464
Table 23-2 List of CAN WAKE up Control Registers
465
List of Message Buffers (ID Registers)
466
Table 23-3 List of Message Buffers (ID Registers)
466
List of Message Buffers (DLC Registers and Data Registers)
468
Table 23-4 List of Message Buffers (DLC Registers)
468
Table 23-5 List of Message Buffers (Data Registers)
469
Classifying CAN Controller Registers
470
Control Status Register (CSR)
471
Fig. 23.2 Node Status Transition Diagram
472
Table 23-6 Correspondence between NS1 and NS0 and Node Status
472
Bus Operation Stop Bit (HALT = 1)
473
Last Event Indicate Register (LEIR)
474
Receive and Transmit Error Counters (RTEC)
475
Bit Timing Register (BTR)
476
Fig. 23.3 Bit Time Segment in CAN Specification
476
Fig. 23.4 Bit Time Segment in CAN Controller
476
Message Buffer Valid Register (BVALR)
478
IDE Register (IDER)
478
Transmission Request Register (TREQR)
479
Transmission RTR Register (TRTRR)
479
Remote Frame Receiving Wait Register (RFWTR)
480
Transmission Cancel Register (TCANR)
480
Transmission Complete Register (TCR)
481
Transmission Interrupt Enable Register (TIER)
481
Reception Complete Register (RCR)
482
Remote Request Receive Register (RRTRR)
482
Receive Overrun Register (ROVRR)
483
Reception Interrupt Enable Register (RIER)
483
Acceptance Mask Select Register (AMSR)
484
Table 23-7 Selection of Acceptance Mask
484
Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
485
Message Buffers
486
ID Register X (X = 0 to 15) (Idrx)
487
DLC Register X (X = 0 to 15) (Dlcrx)
488
Data Register X (X = 0 to 15) (Dtrx)
489
CAN WAKE up Control Register (CWUCR)
490
Transmission of CAN Controller
491
Fig. 23.5 Transmission Flowchart of the CAN Controller
492
Reception of CAN Controller
493
Fig. 23.6 Flowchart Determining Message Buffer (X) Where Receive Messages Stored
494
Reception Flowchart for CAN Controller
495
Fig. 23.7 Reception Flowchart for the CAN Controller
495
How to Use CAN Controller
496
Procedure for Transmission by Message Buffer (X)
497
Procedure for Reception by Message Buffer (X)
499
Fig. 23.8 Example of Receive Interrupt Processing
499
Setting Configuration of Multi-Level Message Buffer
500
Fig. 23.9 Examples of Operation of Multi-Level Message Buffer
501
CAN WAKE up Function
502
Chapter 24 Low Voltage and CPU Operation Detection Reset Circuit
504
Overview of Low Voltage and CPU Operation Detection Reset Circuit
506
Table 24-1 Detection Voltage of Detection Reset Circuit for Low Voltage and CPU Operation
506
Table 24-2 Interval Time for CPU Operation Detection Reset Circuit
506
Configuration of Low Voltage and CPU Operation Detection Reset Circuit
507
Fig. 24.1 Block Diagram of Detection Reset Circuit for Low Voltage and CPU Operation
507
Register for Low Voltage and CPU Operation Detection Reset Circuit
508
Fig. 24.2 Low Voltage and CPU Operation Detection Reset Control Register (LVRC)
508
Table 24-3 Explanation of Function of each Bit of Low Voltage and CPU Operation Detection Reset Control Register
509
Operation of Low Voltage and CPU Operation Detection Reset Circuit
510
Table 24-4 Operation Stabilization Wait Time
510
Cautions When Using Low Voltage and CPU Operation Detection Reset Circuit
511
Sample Program for Low Voltage and CPU Operation Detection Reset Circuit
512
Chapter 25 1-Mbit Flash Memory
514
Overview of 1-Mbit Flash Memory
516
Block Diagram for Entire Flash Memory and Flash Memory Sector Configuration
517
Fig. 25.1 Block Diagram for Entire Flash Memory
517
Fig. 25.2 Sector Configuration of 1-Mbit Flash Memory
518
Program/Erase Mode
519
Table 25-1 Flash Memorr Control Signals
520
Flash Memory Control Status Register (FMCS)
521
Start Automatic Algorithm of Flash Memory
523
Table 25-2 Command Sequence List
523
Check Execution State of Automatic Algorithm
524
Table 25-3 Bit Allocation of Hardware Sequence Flags
524
Table 25-4 List of Functions of Hardware Sequence Flags
524
Data Polling Flag (DQ7)
525
Table 25-5 State Transition of Data Polling Flag (State Change at Normal Operation)
525
Table 25-7 State Transition of Toggle Bit Flag (State Change at Normal Operation)
526
Table 25-8 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
526
Toggle Bit Flag (DQ6)
526
Table 25-10 State Transition of Timing Limit Exceeding Flag (State Change at Abnormal Operation)
527
Table 25-9 State Transition of Timing Limit Exceeding Flag (State Change at Normal Operation)
527
Timing Limit Exceeding Flag (DQ5)
527
Sector Erase Timer Flag (DQ3)
528
Table 25-11 State Transition of Sector Erase Timer Flag (State Change at Normal Operation)
528
Table 25-12 State Transition of Sector Erase Timer Flag (State Change at Abnormal Operation)
528
Details of Programming to and Erasing from Flash Memory
529
Read/Reset State in Flash Memory
529
Data Programming to Flash Memory
530
Fig. 25.3 Example of Data Programming Procedure
531
All Data Erasing from Flash Memory (Chip Erase)
532
Erasing any Data in Flash Memory (Sector Erase)
532
Fig. 25.4 Example of Sector Erasing Procedure
533
Sector Erasing Suspention
534
Sector Erasing Resumption
534
Cautions When Using Flash Memory
535
Sample Program for 1-Mbit Flash Memory
536
Chapter 26 Examples of MB90F428/A Serial Write Connection
542
Basic Configuration of MB90F428/A Serial Write Connection
542
Table 26-1 Pins Used for Fujitsu Standard Serial Onboard Writing
542
Table 26-2 Flash Microcontroller Programmer System Configuration (Manufactured by Yokogawa Digital Computer Ltd.)
543
Example of Serial Write Connection (User Power Supply Used)
544
Fig. 26.1 Example of Serial Write Connection for MB90F428/A (User Power Supply Used)
544
Example of Serial Write Connection (Power Supplied from the Writer)
546
Fig. 26.2 Example of Serial Write Connection for MB90F428/A (Power Supplied from the Writer)
546
Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)
548
(User Power Supply Used)
548
Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the Writer)
550
(Power Supplied from the Writer)
550
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