Nokia 9000i Service Manual page 64

RAE/RAK–1N
Baseband
Coder is used to perform block encoding, decoding, and ciphering
according to GSM algorithms A5 and A5/2.
The ASIC takes care of the interface between the DSP and the RFI: TX
modulator, RX filter, TX and RX sample buffers and controlling state
machine. The interface to RFI is done using 12 bit data bus, 4 bit address
bus, RDX and WRX. There is also data acknowledge (DAX) signal from
RFI to ASIC. Also in this block is the serial RF synthesizer interface
(SCLK, SDAT, SENA1) and the digital RF control signals (RXPWR,
TXPWR, TXP, SYNTHPWR)
Main components
– D2CA ASIC, physically in MCM2
– 2 x TC7S00F (D300,D301) NAND gate
– Transistors BC848W (V330) and BCW30 (V331)
RFI
Introduction
The RFI block consists of the RFI ASIC and its reference voltage
generator. This block is an interface between the RF and baseband
sections. The RFI block has the following functions:
– IF receiving and A/D conversion
– I/Q separation
– I– and Q–transmit and D/A conversion
– AFC D/A conversion
– TXC D/A conversion (burst template)
– analog AGC and digital LNA gain switch
Technical specification
Table 39. External Signals and Connections, Inputs
Signal Name
VL1 Logic supply voltage. Max 150 mA.
VA2 Analog supply voltage. Max 80 mA.
RESETX Master (power up) reset
RFIAD(3:0) RFI address bus
RDX Read strobe
WRX Write strobe
RFICLK RFI master clock
RFI2CLK RFI sleep clock
RXQ RX quadrature signal
RXI RX in–phase signal
Page 2–38
Inverter buffer stage is used for converting the low–level VCXO
clock to valid logic levels.
The SIM power switch.
Signal description
After Sales
Technical Documentation
From
PWRU
PWRU
PWRU
ASIC
ASIC
ASIC
ASIC
ASIC
RF
RF
Original, 08/96