CONTENTS
720T Block diagram .................................................................................... 1-2
Simple AHB transfer.................................................................................... 6-2
Simple memory cycle .................................................................................. 6-5
Level one descriptor.................................................................................... 7-6
Section descriptor ....................................................................................... 7-8
Figure 7-8
Section translation..................................................................................... 7-10
Figure 7-9
Level two descriptor .................................................................................. 7-10
Typical debug system ................................................................................. 9-2
Debug state entry........................................................................................ 9-5
iv
List of Figures
EPSON
ARM720T CORE CPU MANUAL