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Bus status interrupt
The I2CS module provides the status bits listed below to represent the transmit/receive and I
Section 21.5 for details of each function).
1. ASDET/I2CS_STAT register: This bit is set to 1 when the slave address is detected by the asynchronous ad-
dress detection function.
2. TXUDF/I2CS_STAT register: This bit is set to 1 when a transmit operation has started before transmit data
is written. (When the clock stretch function is disabled)
3. DA_NAK/I2CS_STAT register: This bit is set to 1 when a NAK is returned from the master during trans-
mission.
4. DMS/I2CS_STAT register: This bit is set to 1 when the SDA line status is different from transfer data.
DMS will also be set to 1 when another slave device issues ACK to this I
EN/I2CS_CTL register = 0).
Note: When the master device of the I
ing this IC, starts communication with another slave device, the I2CS module issues NAK
in response to the sent slave address. On the other hand, the selected slave device issues
ACK. Therefore, DMS may be set due to a difference between the output value of this IC
and the SDA line status. When SELECTED/I2CS_ASTAT register is set to 0, you can ig-
nore DMS without a problem even if it is set to 1 as there is a difference in the response
code (ACK/NAK) from the selected slave device.
When the I2CS module is placed into asynchronous address detection mode (ASDET_EN
= 1), a DMS does not occur as in the condition above.
5. RXOVF/I2CS_STAT register: This bit is set to 1 when the next data has been received before the received
data is read (the received data is overwritten). (When the clock stretch function is disabled)
6. BFREQ/I2CS_STAT register: This bit is set to 1 when a bus free request is accepted.
7. DA_STOP/I2CS_STAT register: This bit is set to 1 if a stop condition or a repeated start condition is de-
tected while this module is selected as the slave device.
When one of the bits listed above is set to 1, BSTAT/I2CS_STAT register is set to 1 and an interrupt signal is
output to the ITC. An interrupt occurs if other interrupt conditions are satisfied. This interrupt can be used to
perform an error or terminate handling.
Set BSTAT_IEN/I2CS_ICTL register to 1 when using this interrupt. If BSTAT_IEN is set to 0 (default), inter-
rupt requests by this cause will not be sent to the ITC.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
21.7
Control Register Details
address
0x4360
I2CS_TRNS
I
2
C Slave Transmit Data Register
0x4362
I2CS_RECV
I
2
C Slave Receive Data Register
2
0x4364
I2CS_SADRS I
C Slave Address Setup Register
0x4366
I2CS_CTL
I
2
C Slave Control Register
0x4368
I2CS_STAT
I
2
C Slave Status Register
2
0x436a
I2CS_ASTAT
I
C Slave Access Status Register
0x436c
I2CS_ICTL
I
2
C Slave Interrupt Control Register
The I2CS module registers are described in detail below. These are 16-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
S1C17624/604/622/602/621 TeChniCal Manual
2
C bus, which has multiple slave devices connected includ-
Table 21.
7.1 List of I2CS Registers
Register name
Seiko epson Corporation
2
C slave address (when ASDET_
Function
I
2
C slave transmit data
I
2
C slave receive data
2
Sets the I
C slave address.
Controls the I
2
C slave module.
Indicates the I
2
C bus status.
2
Indicates the I
C slave access status.
Controls the I
2
C slave interrupt.
2
21 i
C SlaVe (i2CS)
2
C bus statuses (see
21-9
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