Block Diagram And Schematic Diagram; Block Diagram - Pioneer PRA-BD11 Service Manual

1

3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM

3.1 BLOCK DIAGRAM

A
PRA-BD11
CN8101
BNC
Connector
IC8103
GS9025A
SDI IN
SDI Receiver
B
CN8301
BNC
Connector
IC8301
CS8414-CS
AES/EBU
AES/EBU Receiver
IN
C
Main Device
D
• SDI section
IC
IC8103 (GS9025A) SDI Receiver
IC8108 (GS9020A) SDI Decoder
IC8106 (GS9023A) Audio Processor
• AES/EBU section
IC
E
AES/EBU
IC8301 (CS8414-CS)
Receiver
• Common section
IC
IC8201
FPGA
(XC2S50-5PQ208C)
F
10
1
2
• PCLKOUT (27MHz)
• SDO
• SDO#
• SCO
IC8108
• SCO#
GS9020A
SDI Decoder Audio Processor
• 20 DOUT [0:9]
• PCLKOUT
• 14 SDATA
• 14 FSYNC
• 14 SCK
Control BUS
+5V
IC8306
5V → 3.3V
Regulator
IC8307
5V → 2.5V
Regulator
Name
SDI Receiver receive a SDI signal, and extract the 270MHz clock and equalize the signal.
SDI Decoder receive the output of SDI Receiver, and perform the serial/parallel conversion and
27MHz clock generation.
Audio Processor demultiplex the video/audio signal from the SDI parallel, and each output it.
Name
AES/EBU Receiver receive an AES/EBU signal, and judge a format.
Then generate audio data and output it.
Name
FPGA convert a format of the video signal and the audio signal which extracted from SDI and
AES/EBU signals.
Switching control of 27MHz main clock of PRV-LX1, and the control of each IC.
2
3
IC8106
• 23 DOUT [0:9]
GS9023A
SDI Video
Format det.
Copy protect det.
• AOUTA
• AOUTB
• WCOUT
SDI Audio
Format det.
IC8201
XC2S50-5PQ208C
FPGA
AES/EBU
Format det.
Control
Device etc.
+3.3V
X8301
JTAG BUS
27MHz OSC
+2.5V
IC8205
PE9016A
PROM
Function
Function
Function
PRA-BD11
3
4
Note ;
∗1 : 27MHz clock from PRV-LX1
∗2 : 27MHz clock to PRV-LX1
IC8203
Select
27MHz
Clock Select
MAIN Clock
Digital Video Data
SDI Embedded Digital Audio Data
AES/EBU Digital Audio Data
+5V
GND
4
CN8203
FFC (30P)
∗1
∗2
CN8202
FFC (26P)
CN8201
PH (4P)