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MN 6 6 2 7 8 5 T B U C
D . S e r i a l d a t a o u t p u t t i m i n g
T h e f o l l o w i n g t i m i n g c h a r t s h o w s t h e o u t p u t t i m i n g o f s e r i a l d a t a . S e r i a l d a t a o u t p u t m o d e 1
a n d 2 a r e t h e s a m e i n t h e o u t p u t t i m i n g o f s e r i a l d a t a .
I n v a l i d
S R D A T A
L R C K
B C L K
7-2 (3) Serial data input
When the IC is in serial data output mode 1 or 2, the SRDATA signal, LRCK signal, and BCLK
signal will be input into pins 57, 58, and 59 respectively so that IOSTOP bit will be set to 0.
Therefore, handle pins 57, 58, and 59 as input pins in serial data output mode 1 or 2.
The input timing of serial data is the same as the output timing of serial data.
1 5
14131 2111 0 9 8 7 6 5 4 3 2 1 0
L - c h
Invalid
1 5
S D D 0 0 0 2 6 A E M
I n v a l i d
141 31 21 11 0 9 8 7 6 5 4 3 2 1 0
R-ch
1 5
L-ch
6 4
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