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7 DETAILS OF INSTRUCTIONS
cv.la %rd, %rs
Function
Data conversion from 24 bits to 32 bits
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
1
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
The eight high-order bits of the rs register are transferred to the eight low-order bits of the rd
register. The 16 high-order bits of the rd register are set to 0.
(2) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit.
Example
When the R1 register contains 0x800000
cv.la
7-30
rd(23:8) ← 0, rd(7:0) ← rs(23:16)
9
8
7
|
|
0
1
0
r d
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
23
16 15
rs
8 bits
23
rd
0
0
0
0
0
0
0
0
%r0,%r1
; r0 = 0x000080
Seiko Epson Corporation
6
5
4
3
2
1
0
|
0
1
1
0
r s
|
|
|
|
|
X
8
7
0
0
0
0
0
0
0
0
0
0
0
8 bits
S1C17 CORE MANUAL
(REV. 1.2)
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