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S5U1C33001H
• Parameter file
Make sure the parameter file for the S5U1C33001H is set correctly according to the specifications of the target system.
For details on the parameter file, refer to the "Debugger" section in the "S5U1C33001C Manual (C Compiler Package for
S1C33 Family)".
• Models with cache memory embedded
The debugging operations performed while program execution is suspended rewrite the contents of the cache memory.
Furthermore, the software PC break function cannot be used when the cache is used under conditions other than that
listed in the table below. Use the hardware break function in such cases.
1
2
3
• Models with MMU embedded
The debugging operations performed while program execution is suspended access physical addresses in the default
setting.
Although there are some restrictions, it can be changed so that logical addresses will be accessed. For more informa-
tion, refer to the "Debugger" section in the "S5U1C33001C Manual (C Compiler Package for S1C33 Family)".
Differences from the Actual IC
The S5U1C33001H is different from the actual IC in the way specified below. If this difference is not taken into consideration
in an application, the program may not operate normally in the actual IC.
• Register initialization
When the actual IC is powered on, the contents of all registers except the PC (program counter) and PSR (processor
status register) are indeterminate and retain the immediately preceding values after a reset, whereas in the
S5U1C33001H all registers are initialized when the debugger on the host computer is invoked. At this time, the registers
are initialized with the following data:
For all cores
PSR (processor status register):
AHR, ALR (arithmetic operation high/low registers): 0xAAAAAAAA
R0 through R15 (general-purpose registers):
For C33 STD, Mini and PE cores
PC (program counter):
SP (stack pointer):
For C33 ADV core
PC (program counter):
LCO (loop count register):
LSA (loop start address register):
LEA (loop end address register):
SOR (shift out register):
TTBR (trap table base register):
DP (data pointer):
USP (user stack pointer):
SSP (supervisor stack pointer):
For this reason, never create a program that depends on the initialized value. However, for reset input from the target
system when the target program is being executed, the S5U1C33001H retains the immediately preceding values, as
with the actual IC. For details on each register, refer to the C33 Core Manual.
Note: The PC initial value is decided according to the setting value of the trap table base register (boot address).
Refer to the "S1C33xxx Technical Manual" for details on the trap table base register (TTBR).
22
(Ver. 4)
Table 12 Cache Usage Conditions to Use Software PC Break
Instruction cache
OFF
ON
OFF
ON (write through mode only)
0x00000000
0xAAAAAAAA
(Note)
0x00C00000
0x0AAAAAA8
(Note)
0x20000000
0x00000000
0x00000000
0x00000000
0x00000000
0x20000000
0x00000000
0x00000000
0x00000000
Data cache
OFF
ON
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