I2C Support; Table 3-1 I2Cbus Through E12 - GE VMIVME-7805 Hardware Reference Manual

2
3.2 I C Support
The VMIVME-7805/VME-7805RC support the I
I
Philips Semiconductor. Communication over the I
the use of the National Semiconductor Super I/O I
is capable of communicating on the I
polled handshaking and supports a programmable clock rate when operating in
Master mode. The I
VME-7805RC E12 header as shown in Table 3-1.
Table 3-1 I
The VMIVME-7805/VME-7805RC provide termination on the I
The controller can issue interrupts to the VMIVME-7805/VME-7805RC when
handshaking on the I
active, software must service and then clear the interrupt. Software can determine
the cause of the interrupt by reading the bit of the status register.
For more information related to programming the I
section "Access, Bus Interface (ACB)" in the "PC87366 128-pin LPC Super I/O with
System Hardware Monitoring and MIDI and Game Ports" datasheet available from
National Semiconductor.
40 VMIVME-7805/VME-7805RC Hardware Reference Manual
2
Cbus master or slave per the I
2
Cbus signals are available through the VMIVME-7805/
2
Cbus Through E12
Signal Name
+5.0 V
I2C_SDA
I2C_SCL
GND
2
Cbus. When the I
2
2
Cbus specification, version 2.0, developed by
2
Cbus on a byte-wise basis using interrupt or
Pin
1
2
3
4
2
Cbus controller drives the interrupt
Cbus and can operate as an
2
Cbus is accomplished through
2
Cbus controller. This controller
2
C signals.
2
Cbus controller, see the