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No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any lia-...
S2D13515 Display Controller. The S5U13515P00C100 evaluation board can be used with many native platforms via the host connector which provides the appropriate signals to support a variety of CPUs. The S5U13515P00C100 evaluation board can also connect to the S5U13U00P00C100 USB Adapter board so that it can be used with a laptop or desktop computer, via USB 2.0.
Chapter 2 Features Chapter 2 Features The S5U13515P00C100 Evaluation Board includes the following features: • 256-pin PBGA S2D13515 Display Controller • On-board SDRAM, configurable as 32MB (32-bit wide) or 16MB (16-bit wide) • On-board Serial Flash Memory, 32Mbit • Headers for connection to various Host Bus Interfaces (includes all S2D13515 Host Bus Interface signals) •...
Chapter 3 Installation and Configuration Chapter 3 Installation and Configuration The S5U13515P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm resistors which allow it to be used with a variety of different configurations. 3.1 CNF[7:0] Configuration Inputs The S2D13515 has 8 configuration inputs (CNF[7:0]), which can be configured through a combination of a DIP switch and 0 ohm resistors.
CNF3 and CNF6 are mapped to different pins depending on the combination of the other CNF inputs. The following figure shows the location of the 0 Ohm resistors used to configure CNF[7:3]. Figure 3-2: CNF[7:3] 0 Ohm Resistor Locations EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
3.1.3 Host Interface Configuration The host bus interface used by the S5U13515P00C100 evaluation board is selected using a combination of the CNF[2:1] pins and unused host interface pins. Many host bus interfaces have unused pins that can be used as config- uration pins (CNF[7:3]) to select the host bus interface.
Chapter 3 Installation and Configuration 3.2 Configuration Jumpers The S5U13515P00C100 has 16 jumpers which configure various evaluation board settings. The jumper positions for each function are shown below. Table 3-4: Configuration Jumper Settings Jumper Function Position 1-2 Position 2-3 No Jumper...
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JP5 for PIO1VDD JP6 for HIOVDD JP10 for CM1VDD JP11 for PIO2VDD JP14 for IOVDD JP15 for SDVDD Figure 3-3: Configuration Jumper Locations (JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, JP15) S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON...
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When the jumper is at position 1-2, the PIO1VDD voltage must be provided to pin 9 on the H9 connector. When the jumper is at position 2-3, the PIO1VDD voltage is provided by the 3.3V power supply of the board. Figure 3-5: Configuration Jumper Location (JP8) EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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When the jumper is at position 1-2, the CM1VDD voltage must be provided to pin 8 on the H9 connector. When the jumper is at position 2-3, the CM1VDD voltage is provided by the 3.3V power supply of the board. Figure 3-7: Configuration Jumper Location (JP12) S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON...
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When the jumper is at position 2-3, the external SDRAM is 16 bits wide and the memory size is 16M bytes. In this configuration, one memory chip is disabled and only one chip is active (16M bytes and 16 bits wide). Figure 3-9: Configuration Jumper Location (JP16) EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
4.1 Power 4.1.1 Power Requirements The S5U13515P00C100 evaluation board requires an external regulated power supply (3.3V / 1A). The power is supplied to the evaluation board through pin 33 of the H4 header, or pin 5 of the P2 header.
The clock for the S2D13515 Display Controller is provided by a 20MHz crystal connected to the OSCI and OSCO pins. Additionally, the S5U13515P00C100 evaluation board can also use an oscillator if the DIP14 footprint is populated. If populated, the oscillator is connected to the CLKI input clock of the S2D13515 Display controller.
4.5.1 Direct Host Bus Interface Support All S2D13515 host interface pins are available on connectors H3 and H4. This allows the S5U13515P00C100 evalu- ation board to be connected to a variety of development platforms. For S2D13515 host interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
When the S5U13515P00C100 is connected to the S5U13U00P00C100 USB Adapter board, there are 2 LEDs on the S5U13515P00C100 which provide a quick visual status of the USB adapter. LED1 blinks to indicate that the USB adapter board is active. LED2 turns on to indicate that the USB has been enumerated by the PC.
Functional Specification, document number X83A-A-001-xx. 4.6.2 FP2IO Interface All FP2IO interface signals are available on connectors H5 and H7. For S2D13515 FP2IO interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx. S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON...
Connector H10 is a 0.1” x 0.1”, 20-pin header (10 x 2). The following figure shows the location of the connector H10. Figure 4-5: Camera Connector Location (H10) For the pinout of connector H10, see Section Chapter 6, “Schematic Diagrams” on page 29. EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
The S2D13515 Display Controller can support up to a 5x5 matrix keypad, but the S5U13515P00C100 evaluation board includes only a 3x3 keypad. The keypad interface can be configured to use either the FPIO1 interface or Host interface pins.
Connector H8 is a 0.1” x 0.1”, 24-pin header (12x2). The following figure shows the location of the connector H8. Figure 4-7: I2S Connector Location (H8) For the pinout of connector H8, see Section Chapter 6, “Schematic Diagrams” on page 29. EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
The S2D13515 Display Controller has two PWM outputs which are available on connector H9. The other pins on connector H9 are used to connect the external power supplies to CM1VDD, IOVDD, PIO1VDD, and PIO2VDD, if a voltage level different than 3.3V is required. Note that connector H9 is not populated on the S5U13515P00C100 evaluation board.
R63, R209 not populated S5U13515P00C100 board comes configured for the C33 Debugger port from the Host Interface AB[11:6] pins, so resistors R63, R65 ~ R69 are populated and R197 ~ R202 are not populated, R203 ~ R215 are populated and R64, R70 ~ R81 are not populated.
The S2D13515 Display Controller has a JTAG interface. All the JTAG signals are available on connector H1. Note that connector H1 is not populated on the S5U13515P00C100 evaluation board. Connector H1 is a 0.1” x 0.1”, 12-pin header (6x2). The following figure shows the location of the connector H1.
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SDRAM 128Mb x 16-bit x 4 128Mb x 16-bit x 4 128Mb x 16-bit x 4 128Mb x 16-bit x 4 banks banks banks banks Figure 6-2: S5U13515P00C100 Schematics (2 of 5) EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)