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HP Net Vectra Technical Reference Manual

Hp net vectra: reference manual
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Technical Reference Manual
Hardware and BIOS
HP Net Vectra PC

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Summary of Contents for HP Net Vectra

  • Page 1 Technical Reference Manual Hardware and BIOS HP Net Vectra PC...
  • Page 2 Adobe Systems Incorporated which may be registered in certain jurisdictions. Microsoft®, Windows® and MS-DOS® are U.S. registered trademarks of Microsoft Corporation. Pentium® is a U.S. registered trademark of Intel Corporation. Hewlett-Packard France Commercial Desktop Computing Division 38053 Grenoble Cedex 9 France 1997 Hewlett-Packard Company...

  • Page 3: Conventions

    Preface This manual is a technical reference and BIOS document for engineers and technicians providing system level support. It is assumed that the reader possesses a detailed understanding of AT-compatible microprocessor functions and digital addressing techniques. Technical information that is readily available from other sources, such as manufacturer’s proprietary publications, has not been reproduced.

  • Page 4: Bibliography

    Bibliography HP Net Vectra User’s Guide (D5470-90001). HP Net Vectra Upgrading and Maintaining the PC (available on WWW). HP Net Vectra Recovery Guide (available on WWW). HP Net Vectra Familiarization Guide (D5470-90901). HP Net Vectra Online User’s Guide (online). Exploring your HP Net Vectra PC (online).

  • Page 5: Table Of Contents

    Contents Preface ..........Conventions .
  • Page 6 4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS Summary ....... . . 44 Setup Program .
  • Page 7 Product Identification........HP I/O Port Map (I/O Addresses Used by the System)....
  • Page 8 Contents viii...

  • Page 9: System Overview

    System Overview This manual describes the HP Net Vectra PC, and provides detailed system specifications. This chapter introduces the external features, and summarizes the documentation which is available.

  • Page 10: Package

    1 System Overview Package Package Front view Cover lock Front view with cover removed Main memory Processor System board switches Heat-pipe and Heat-sink Rear view (All icons shown here are for information, and do not necessarily appear on the PC). On/off button Pause button Status light...

  • Page 11: Documentation

    Documentation The table below summarizes the availability of documentation that is appropriate to the HP Net Vectra PC. Most are available as viewable files (which can also be printed) from the HP division support servers, and on the HP Support Assistant CD-ROM.

  • Page 12: Where To Find The Information

    Where to Find the Information The following table summarizes the availability of information within the HP Net Vectra PC documentation set. The user is supplied with the online documentation preloaded on the PC, and the User’s Guide (in paper form).
  • Page 13 User Documentation User’s Guide Configuring devices Peripherals Network Problem fixes The Setup program Key fields Troubleshooting Basic Advanced New symptoms Service notes Technical information Basic Detailed Advanced System board Jumpers & Switches Connectors Replacement Chip-set BIOS Basic details Technical details Memory maps Upgrading Power-On Self-Test...
  • Page 14 1 System Overview Documentation...

  • Page 15: System Board

    System Board The next chapter describes the graphics, disk and network devices which are supplied with the computer. This chapter describes the components of the system board, taking in turn the components of the Processor-Local Bus, the Peripheral Component Interconnect (PCI) bus and the Industry Standard Architecture (ISA) bus.

  • Page 16: System Board

    2 System Board System Board System Board Voltage Regulator Status Panel Connector L2 cache PCI wake-up connector SiS 5581 PL/PCI bridge, PCI/ISA bridge, DRAM controller, IDE+USB cntlr NS87317 Super I/O controller Graphics Controller Chip System ROM Parallel Port Serial Port System Board Switches Ext.

  • Page 17: Architectural View

    Serial Interrupt EEPROM controller ISA bus interface Pentium processor Graphics controller NS87317 X Ben Super I/O (HP ASIC) Keyboard controller controller Parallel controller controller System 2 serial interface controller 2 System Board Architectural View Processor-Local Bus (64 bit, 66 MHz)

  • Page 18: Chip-Set

    2 System Board Chip-Set Chip-Set The chip-set comprises two chips. These interface between the three main buses (the Processor-Local bus, the PCI bus and the ISA bus). • The Bridge chip (SiS5581) is a combined PL/PCI bridge and cache controller and main memory controller and PCI/ISA bridge and IDE controller and USB controller.
  • Page 19 Level-2 Cache Memory The Level-2 cache memory controller supports either write through or write back direct mapped pipelined burst static RAM. On the HP Net Vectra Controller PC, 256KB of write back cache memory is implemented as two 32K chips soldered on the system board.

  • Page 20: Super I/O Chip (Ns87317)

    2 System Board Chip-Set arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing pattern. When the banks have been filled contiguously (bank A, then bank B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2 timing pattern. IDE Controller The PCI master/slave IDE controller, supporting four devices, two on each of two channels, is described on page 26.
  • Page 21 Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible). Enhanced mode (enhanced parallel port, EPP, compatible). High speed mode (MS/HP extended capabilities port, ECP, compatible). The integrated flexible drive controller (FDC) supports any combination of two from the following: tape drives, 3.5-inch flexible disk drives, 5.25-inch flexible disk drives.
  • Page 22 General Purpose I/O There are several general purpose I/O pins. Some of these are used on the HP Net Vectra to sense the current settings of system board switches (as described on page 24 and page 31). Cache-sleep...
  • Page 23 Description Enable RPO Flash page select Bus core frequency BCF2 (connected to SW-5, always 1) POR# (ExtSMI) Flash program enable (FLASHLOCK) Backplane ID0 (always 1) Backplane ID1 (always 1) Bus core frequency BCF0 (connected to SW-3, open=1, closed=0) Bus core frequency BCF1 (connected to SW-4, open=1, closed=0) Host bus request detect (60/66 MHz) (connected to SW-1, always 0) Serial EEPROM data FDD write protect (not used)

  • Page 24: Devices On The Processor-Local Bus

    You will not need to change the switches if you upgrade the original processor using the correct Intel Overdrive. No other types of processor upgrade are supported by HP.

  • Page 25: Cache Memory

    8 KB. The L2 cache memory is controlled by the Bridge chip in the system board chip-set. On the HP Net Vectra PC, 256 KB of direct mapped, write-back, synchronous pipelined burst, 8.5 ns static random access memory (SRAM) is integrated on the system board.

  • Page 26: Devices On The Pci Bus

    2 System Board Devices on the PCI Bus Devices on the PCI Bus PCI Device Device Name PL/PCI bridge PCI/ISA bridge IDE controller USB controller Integrated graphics controller S3 Trio 64V2 PCI slot #1 PCI slot #2 The distribution of the interrupt lines is described more fully on page 59. Integrated Drive Electronics (IDE) The IDE controller is implemented as part of the Bridge chip.
  • Page 27 The three DMA modes (for single or double word) allow the following transfer rates: Mode Cycle time (ns) Transfer rate (MB/s) The three Ultra ATA/33 modes (also know as Ultra DMA modes) allow the following peak transfer rates: Mode Cycle time (ns) Transfer rate (MB/s) Disk Capacity Versus The amount of addressable space on a hard disk is limited by three factors:...

  • Page 28: Universal Serial Bus (Usb) Controller

    • Supports daisy-chaining through a tiered-star, multi-drop topology (up to 6 tiers) USB works only if the USB interface has been enabled within the HP Setup program. Currently, only the Microsoft Windows 95 operating system provides support for the USB.

  • Page 29: Devices On The Isa Bus

    Devices on the ISA Bus ISA Device Index Super I/O X Ben (HP ASIC) 496h Super I/O Controller The Super I/O chip (NS87317) is part of the chip set, and is described on page 20. The computer is supplied with a Logitech 2-button mouse, and a keyboard...
  • Page 30 Chapters 4 and 5. Updating the System ROM The System ROM can be updated with the latest BIOS. This can be downloaded, as a compressed file, from the HP Electronic Services ). You must specify the model of the computer http://www.hp.com/go/vectrasupport since the utility which is supplied for a different model cannot be used with this one.
  • Page 31 Do not switch off the computer until the system BIOS update procedure has completed, successfully or not. To do so could cause irrecoverable damage to the ROM, thereby requiring the replacement of the system board. The control panel switches are automatically disabled to prevent accidental interruption of the flash programming process, but this, of course, does not protect against deliberate or inadvertent removal of the power cord, or other types of power failure, however caused.

  • Page 32: X-Ben

    X-Ben X-Ben is an HP application specific integrated circuit (ASIC), designed to be a companion to the Super I/O chip. It is described on page 51. position, not only is the configuration...

  • Page 33: Interface Devices And Mass-Storage Drives

    Interface Devices and Mass-Storage Drives This chapter describes the graphics, mass storage and network devices which are supplied with the computer. It also summarizes the pin connec- tions on the internal and external connectors.

  • Page 34: S3 Trio 64V2 Graphics Controller Chip

    3 Interface Devices and Mass-Storage Drives S3 Trio 64V2 Graphics Controller Chip S3 Trio 64V2 Graphics Controller Chip All models are supplied with a graphics controller chip integrated on the system board. This 64-bit PCI Ultra VGA graphics controller can be characterized as follows: •...
  • Page 35 Interface Mode No. Standard Type text 00h* text 00h+ text text 01h* text 01h+ text text 02h* text 02h+ text text 03h* text 03h+ text graphics graphics graphics text 07h+ text graphics graphics graphics graphics graphics graphics graphics The extended modes supported by the video BIOS are listed in the table on the following page.

  • Page 36: Extended Video Modes

    3 Interface Devices and Mass-Storage Drives S3 Trio 64V2 Graphics Controller Chip Extended Video Modes Extended VESA Interface Resolution Mode No. Mode No. Type 207h graphics 208h graphics 1280 x 1024 212h graphics 213h graphics 10Ah text 132 x 43 chars 109h text 132 x 25 chars...
  • Page 37 Extended VESA Interface Mode No. Mode No. Type 111h graphics 111h graphics 111h graphics 111h graphics 112h graphics 112h graphics 112h graphics 112h graphics 113h graphics 113h graphics 113h graphics 113h graphics 114h graphics 114h graphics 114h graphics 114h graphics 115h graphics 115h...

  • Page 38: Available Video Resolutions

    3 Interface Devices and Mass-Storage Drives S3 Trio 64V2 Graphics Controller Chip Available Video Resolutions The following table lists the available video resolutions using the current drivers. The available resolutions may be different with later versions of driver. Resolution Windows NT 640 x 480 800 x 600 1024 x 768...

  • Page 39: Mass-Storage Drives

    Mass-Storage Drives A 3.5-inch hard disk drive is supplied on an internal shelf in all models. The IDE controller is described on page 26. HP product number Manufacturer 3 Interface Devices and Mass-Storage Drives 1.6 GB IDE 1 GB IDE...

  • Page 40: Connectors And Sockets

    3 Interface Devices and Mass-Storage Drives Connectors and Sockets Connectors and Sockets IDE Hard Disk Drive Data Connector Signal Signal Reset# Ground HD10 HD11 HD12 HD13 HD14 HD15 Ground orientation key DMARQ Ground DIOW# Ground DIOR# Ground IORDY SPSYNC:CSEL DMACK# Ground INTRQ IOCS16#...
  • Page 41 Signal Signal -12 V TRST# +12 V Ground +5 V +5 V +5 V INTA# INTB# INTC# INTD# +5 V Ground reserved reserved PRSNT# +3.3 V reserved orientation key orientation key reserved reserved Ground RESET# +3.3 V Ground GNT# REQ# Ground +3.3 V reserved...

  • Page 42: Vga Connector

    3 Interface Devices and Mass-Storage Drives Connectors and Sockets Power Supply Connector for System Board PwrGood orientation key Remote_On Ground Ground Ground +12 V supply VBATT orientation key Socket Pin Layouts RJ-45 UTP Connector Keyboard and Mouse Connector Serial Port Connector Signal Signal +5 Vstdby...

  • Page 43: Summary Of The Hp/Phoenix Bios

    Summary of the HP/Phoenix BIOS The Setup program and HP/Phoenix BIOS are summarized in this chapter. The POST routines are described in the next chapter.

  • Page 44: Hp/Phoenix Bios Summary

    4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS Summary HP/Phoenix BIOS Summary The System ROM contains the POST (power-on self-test) routines, and the BIOS: the System BIOS, video BIOS, network BIOS, and low option ROM. This chapter, and the following one, give an overview of the following aspects: •...
  • Page 45 : N o t I n s t a l l e d <F1> to continue, <F2> to run Setup, <F10> to power off, <F5> to retain 4 Summary of the HP/Phoenix BIOS P C S e r i a l N um b e r...

  • Page 46: Setup Program

    4 Summary of the HP/Phoenix BIOS Setup Program Setup Program To run the Setup program, interrupt the POST by pressing when the initial “Vectra” logo screen is being displayed, just after restarting the PC. The band along the top of the screen offers five menus: Main, Configuration, Security, Power, and Exit.

  • Page 47: Security Menu

    4 Summary of the HP/Phoenix BIOS Setup Program Security Menu Sub-menus are presented for changing the characteristics and values of the User Password, the System Administrator Password, the amount of protection against use of the system’s drives and network connections (using the Hardware Protection sub-menu), and the amount of protection against being able to boot from the system’s drives and network connections...

  • Page 48: Power Saving And Ergonometry

    300 attributes of the PC (both the local PC, and remote ones over the network). HP Lock HP Lock provides a convenient and dynamic access to the security features of the PC. Facilities are provided for: • Passwords •...

  • Page 49: Power-On From Space-Bar

    If the user attempts to turn the PC off at the status panel, the PC logic will delay the shutting down of the power supply until it is safe to do so. HP Off protects the user from some types of unintentional data loss, providing a safe shutdown of running applications and unsaved files.

  • Page 50: Remote Power-On (Rpo)

    16 times and encoded in a valid network packet. Any Magic Packet-compatible management application (such as HP Open- View Workgroup Node Manager) can send a Magic Packet frame. An administrator can do this manually, or can incorporate it into a management script.
  • Page 51 Since the user is not physically present, the level of security must be tighter. There is a distinction between the user-boot process, and the RPO-boot process. HP provides all the necessary Setup options to keep users from interfering with the computer during the remote session.

  • Page 52: Advanced Power Management (Apm)

    4 Summary of the HP/Phoenix BIOS Power Saving and Ergonometry • glue logic (such as programmable chip selects) The computer can be turned on by typing the space-bar on the keyboard, or when it receives an external signal from a network board. When VccState...
  • Page 53 4 Summary of the HP/Phoenix BIOS Power Saving and Ergonometry...
  • Page 54 4 Summary of the HP/Phoenix BIOS Power Saving and Ergonometry The following diagram gives a more accurate, more detailed account of the valid state changes.

  • Page 55: Bios Addresses

    BIOS Addresses This section provides a summary of the main features of the HP system BIOS. This is software that provides an interface between the computer hardware and the operating system. System Memory Map Any reserved memory that is used by accessory boards must be located in the area from C8000h to EFFFFh.

  • Page 56: Hp I/O Port Map (I/O Addresses Used By The System)

    4 Summary of the HP/Phoenix BIOS BIOS Addresses HP I/O Port Map (I/O Addresses Used by the System Peripheral devices, accessory devices and system controllers are accessed via the system I/O space, which is not located in system memory space. The 64 KB of addressable I/O space comprises 8-bit and 16-bit registers (called I/O ports) located in the various system components.

  • Page 57: Hardware Configuration

    The system controller supports seven DMA channels, each with a page register used to extend the addressing range of the channel to 16 MB. The following table summarizes how the DMA channels are allocated. 4 Summary of the HP/Phoenix BIOS BIOS Addresses...
  • Page 58 4 Summary of the HP/Phoenix BIOS BIOS Addresses First DMA controller (used for 8-bit transfers) Channel Available ECP mode for parallel port (available if not used) Flexible disk controller ECP mode for parallel port (available if not used) Second DMA controller (used for 16-bit transfers)
  • Page 59 (which is part of the PCI/ISA bridge, in the Bridge chip). Since most PCI devices are single-function, this allows for an even distribution of the lines. The distribution is shown in the following diagram. 4 Summary of the HP/Phoenix BIOS Available Reserved (used by the DHCP)
  • Page 60 4 Summary of the HP/Phoenix BIOS BIOS Addresses Integrated Slot 1 graphics A B C D PCI interrupts are then mapped into ISA interrupts inside the Bridge chip, by configuring registers 60h through 63h. Slot 2 A B C D Routing of interrupts: when enabled, this bit routes the PCI interrupt signal to the PC- compatible interrupt signal specified in bits[3:0].

  • Page 61: Power-On Self-Test And Error Messages

    Power-On Self-Test and Error Messages This chapter describes the Power-On Self-Test (POST) routines, which are contained in the System BIOS, the error messages that can result, and the suggestions for corrective action.

  • Page 62: Order In Which The Tests Are Performed

    5 Power-On Self-Test and Error Messages Order in Which the Tests are Performed Order in Which the Tests are Performed Each time the system is powered on, or a reset is performed, the POST is executed. The POST process verifies the basic functionality of the system components and initializes certain system parameters.
  • Page 63 Tests the system ROM BIOS and shadows it. Failure to shadow the ROM BIOS will cause an error code to display. The boot process will continue, but Shadow the System ROM BIOS the system will execute from ROM. This test is not performed after a soft reset (using Checks the serial EEPROM and returns an error code if it has been Load CMOS Memory...
  • Page 64 5 Power-On Self-Test and Error Messages Order in Which the Tests are Performed Tests protected RAM in 64 KB segments above 1 MB. (This test is not done Protected Mode RAM Test during a reset using (Extended RAM) error code to display. Keyboard / Mouse Tests Invokes a built-in keyboard self-test of the keyboard’s microprocessor and Keyboard Test...

  • Page 65: Error Message Summary

    Error Message Summary The POST section of the HP BIOS no longer displays numeric error codes (such as 910B) but gives a self-explanatory, descriptive diagnosis, and a list of suggestions for corrective action. The following table summarizes the most significant of the problems that can be reported.

  • Page 66: Beep Codes

    5 Power-On Self-Test and Error Messages Beep Codes Beep Codes If a terminal error occurs during POST, the system issues a beep code before attempting to display the error. Beep codes are useful for identifying the error when the system is unable to display the error message. Beep Numeric Beep Pattern...

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