HP 330 Service Information Manual page 100

Bus Architecture
Introduction
Two or three bus systems are used between the processor boards and memory or accessories
and interfaces:
• System Bus - for fast RAM read/write cycles, Model 350 only.
• DIO Bus for I/O operations with earlier Series 200/300 accessory cards.
• DIO-II Bus -- for better I/O operations with the newer Model
~{30/350
interface and video
boards.
Model 350 System Bus
Memory boards are tightly coupled to the Model 350 processor through a high-speed system
bus. This allows much faster memory cycles and more RAM on memory boards. The system
bus supports 32-bit addresses and data increasing maximum possible memory address space to
4 Gbytes. Synchronous to the processor clock, it supports a write cycle, a read cycle, and a
quad-read cycle.
A 2-s10t system bus connects the Model 350 processor to one RAM controller board and support
up to 16 Mbytes of RAM. When the second RAM controller board is added for more than 16
Mbytes of RAM, the 3-s10t system bus connects the processor board to both 4 Mbyte RAM
controller boards.
Model 330 computers do not use the system bus. Memory cycles in the Model 330 will be slower
than the Model 350.
010 and 010-11 Bus
The standard 16-bit DIO (also used in the Model 310 and 320 computers) is used: all existing
Series 300 I/O cards will function normally. In addition, new I/O boards are supported on
DIO-II. DIO-II extends additional signal lines to some system slots, which allow 32-bit address
and data transfer.
DIO-II supports standard Series 300 system size boards, as well as the newer 32-bit system
boards. It is an extension of the DIO bus used on Model 310/320 computers. In the system
slots, a second connector has been added that carries eight additional address lines, 16 additional
data lines, and several new control signals. The processor drives the lower 23 address bits on
DIO address lines, and drives the upper eight bits on the new address lines. The most significant
sixteen bits of data are transferred on DIO lines, and the least significant 16 bits are transferred
on DIO-II lines.
When the Model 350 processor is not performing I/O cycles, it does not need the DIO /DIO-II
bus at all. Another bus master could obtain control of the bus while the processor continues
running, using the system bus. This parallelism should allow very high throughput with DMA.
However, memory circuits on the Model 350 processor board are connected to the system bus
and not the DIO bus. Since the processor uses this bus to access the RAM, they are not available
to external bus masters. In other words, only the CPU can access the Boot ROMs, MC6840
timer, self-test LED's, and MMU control registers.
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Functional Description