Motorola DSP56000 Manuals

Manuals and User Guides for Motorola DSP56000. We have 2 Motorola DSP56000 manuals available for free PDF download: Manual, Manual 

Motorola DSP56000 Manual

Motorola DSP56000 Manual (637 pages)

24-bit Digital Signal Processor  
Brand: Motorola | Category: Processor | Size: 2.16 MB
Table of contents
Table Of Contents3................................................................................................................................................................
Introduction14................................................................................................................................................................
Origin Of Digital Signal Processing14................................................................................................................................................................
Analog Signal Processing15................................................................................................................................................................
Digital Signal Processing16................................................................................................................................................................
Summary Of Dsp56k Family Features21................................................................................................................................................................
Dsp Hardware Origins21................................................................................................................................................................
Manual Organization23................................................................................................................................................................
Dsp56k Central Architecture Overview25................................................................................................................................................................
Data Buses26................................................................................................................................................................
Address Buses26................................................................................................................................................................
Data Alu27................................................................................................................................................................
Address Generation Unit27................................................................................................................................................................
Program Control Unit27................................................................................................................................................................
Memory Expansion Port (port A)30................................................................................................................................................................
On-chip Emulator (once)30................................................................................................................................................................
Phase-locked Loop (pll) Based Clocking30................................................................................................................................................................
Data Arithmetic Logic Unit33................................................................................................................................................................
Overview And Data Alu Architecture33................................................................................................................................................................
Dsp56k Block Diagram34................................................................................................................................................................
Mac Unit37................................................................................................................................................................
Data Alu Accumulator Registers38................................................................................................................................................................
Data Representation And Rounding40................................................................................................................................................................
Saturation Arithmetic40................................................................................................................................................................
Integer-to-fractional Data Conversion41................................................................................................................................................................
Limited Data Values41................................................................................................................................................................
Bit Weighting And Alignment Of Operands42................................................................................................................................................................
Integer/fractional Number Comparison43................................................................................................................................................................
Integer/fractional Multiplication Comparison44................................................................................................................................................................
Convergent Rounding45................................................................................................................................................................
Double Precision Multiply Mode46................................................................................................................................................................
Full Double Precision Multiply Algorithm46................................................................................................................................................................
Data Alu Programming Model49................................................................................................................................................................
Data Alu Summary49................................................................................................................................................................
Dsp56k Programming Model49................................................................................................................................................................
Address Generation Unit And Addressing Modes53................................................................................................................................................................
Agu Architecture53................................................................................................................................................................
Agu Block Diagram55................................................................................................................................................................
Programming Model56................................................................................................................................................................
Agu Programming Model57................................................................................................................................................................
Addressing58................................................................................................................................................................
Address Register Indirect Summary58................................................................................................................................................................
Address Register Indirect — No Update60................................................................................................................................................................
Address Register Indirect — Postincrement61................................................................................................................................................................
Address Register Indirect — Postdecrement62................................................................................................................................................................
Address Register Indirect — Postincrement By Offset Nn63................................................................................................................................................................
Address Register Indirect — Postdecrement By Offset Nn64................................................................................................................................................................
Address Register Indirect — Indexed By Offset Nn65................................................................................................................................................................
Address Register Indirect — Predecrement66................................................................................................................................................................
Address Modifier Summary68................................................................................................................................................................
Circular Buffer69................................................................................................................................................................
Linear Addressing With A Modulo Modifier70................................................................................................................................................................
Modulo Modifier Example71................................................................................................................................................................
Bit-reverse Addressing Sequence Example73................................................................................................................................................................
Bit-reverse Address Calculation Example74................................................................................................................................................................
Overview79................................................................................................................................................................
Program Address Generator79................................................................................................................................................................
Program Control Unit (pcu) Architecture81................................................................................................................................................................
Three-stage Pipeline83................................................................................................................................................................
Program Control Unit Programming Model84................................................................................................................................................................
Status Register Format85................................................................................................................................................................
Omr Format90................................................................................................................................................................
Stack Pointer Register Format91................................................................................................................................................................
Sp Register Values92................................................................................................................................................................
Dsp56k Central Processing Module Programming Model94................................................................................................................................................................
Instruction Set Introduction97................................................................................................................................................................
Syntax97................................................................................................................................................................
Instruction Formats97................................................................................................................................................................
General Format Of An Instruction Operation Word99................................................................................................................................................................
Operand Sizes100................................................................................................................................................................
Reading And Writing The Alu Extension Registers101................................................................................................................................................................
Reading And Writing The Address Alu Registers101................................................................................................................................................................
Reading And Writing Control Registers102................................................................................................................................................................
Special Addressing – Immediate Data110................................................................................................................................................................
Special Addressing – Absolute Addressing111................................................................................................................................................................
Special Addressing – Short Jump Address113................................................................................................................................................................
Instruction Groups114................................................................................................................................................................
Special Addressing – Absolute Short Address114................................................................................................................................................................
Special Addressing – I/o Short Address115................................................................................................................................................................
Hardware Do Loop119................................................................................................................................................................
Nested Do Loops121................................................................................................................................................................
Classifications Of Parallel Data Moves121................................................................................................................................................................
Parallel Move Examples122................................................................................................................................................................
Processing States125................................................................................................................................................................
Normal Processing State127................................................................................................................................................................
Instruction Pipelining127................................................................................................................................................................
Exception Processing State (interrupt Processing)134................................................................................................................................................................
Fast And Long Interrupt Examples137................................................................................................................................................................
Interrupt Priority Register (addr X:$ffff)138................................................................................................................................................................
Status Register Interrupt Mask Bits138................................................................................................................................................................
Interrupt Priority Level Bits139................................................................................................................................................................
External Interrupt139................................................................................................................................................................
Central Processor Interrupt Priorities Within An Ipl139................................................................................................................................................................
Interrupt Sources140................................................................................................................................................................
Interrupting An Swi141................................................................................................................................................................
Illegal Instruction Interrupt Serviced By A Fast Interrupt143................................................................................................................................................................
Illegal Instruction Interrupt Serviced By A Long Interrupt144................................................................................................................................................................
Repeated Illegal Instruction145................................................................................................................................................................
Trace Exception147................................................................................................................................................................
Fast Interrupt Service Routine151................................................................................................................................................................
Two Consecutive Fast Interrupts152................................................................................................................................................................
Long Interrupt Service Routine154................................................................................................................................................................
Jsr First Instruction Of A Fast Interrupt155................................................................................................................................................................
Jsr Second Instruction Of A Fast Interrupt156................................................................................................................................................................
Reset Processing State157................................................................................................................................................................
Interrupting An Rep Instruction158................................................................................................................................................................
Interrupting Sequential Rep Instructions159................................................................................................................................................................
Wait Processing State160................................................................................................................................................................
Wait Instruction Timing160................................................................................................................................................................
Stop Processing State161................................................................................................................................................................
Simultaneous Wait Instruction And Interrupt161................................................................................................................................................................
Stop Instruction Sequence162................................................................................................................................................................
Stop Instruction Sequence Followed By Irqa163................................................................................................................................................................
Stop Instruction Sequence Recovering With Reset166................................................................................................................................................................
Port A Overview170................................................................................................................................................................
Port A Interface170................................................................................................................................................................
Port A Signals171................................................................................................................................................................
Pll Clock Oscillator Introduction178................................................................................................................................................................
Pll Components178................................................................................................................................................................
Pll Control Register (pctl)181................................................................................................................................................................
Multiplication Factor Bits Mf0-mf11181................................................................................................................................................................
Division Factor Bits Df0-df3182................................................................................................................................................................
Pstp And Pen Relationship184................................................................................................................................................................
Clock Output Disable Bits Cod0-cod1184................................................................................................................................................................
Pll Pins185................................................................................................................................................................
Pll Operation Considerations187................................................................................................................................................................
On-chip Emulation Introduction193................................................................................................................................................................
On-chip Emulation (once) Pins193................................................................................................................................................................
Once Block Diagram193................................................................................................................................................................
Chip Status Information195................................................................................................................................................................
Once Controller And Serial Interface196................................................................................................................................................................
Once Command Register197................................................................................................................................................................
Once Register Addressing197................................................................................................................................................................
Once Status And Control Register (oscr)199................................................................................................................................................................
Memory Breakpoint Control Table200................................................................................................................................................................
Once Memory Breakpoint Logic201................................................................................................................................................................
Once Trace Logic203................................................................................................................................................................
Once Trace Logic Block Diagram204................................................................................................................................................................
Methods Of Entering The Debug Mode205................................................................................................................................................................
Pipeline Information And Global Data Bus Register206................................................................................................................................................................
Once Pipeline Information And Gdb Registers207................................................................................................................................................................
Program Address Bus History Buffer208................................................................................................................................................................
Once Pab Fifo208................................................................................................................................................................
Serial Protocol Description209................................................................................................................................................................
Dsp56k Target Site Debug System Requirements210................................................................................................................................................................
Using The Once210................................................................................................................................................................
User Support221................................................................................................................................................................
Motorola Dsp Product Support222................................................................................................................................................................
Dsp56kadsx Application Development System224................................................................................................................................................................
Dr. Bub Electronic Bulletin Board225................................................................................................................................................................
Motorola Dsp News234................................................................................................................................................................
Motorola Field Application Engineers234................................................................................................................................................................
Design Hotline– 1-800-521-6274234................................................................................................................................................................
Dsp Help Line – (512) 891-3230234................................................................................................................................................................
Marketing Information– (512) 891-2030234................................................................................................................................................................
Third-party Support Information – (512) 891-3098234................................................................................................................................................................
University Support – (512) 891-3098234................................................................................................................................................................
Training Courses – (602) 897-3665 Or (800) 521-6274235................................................................................................................................................................
Reference Books And Manuals235................................................................................................................................................................
A.1 Appendix A Introduction269................................................................................................................................................................
A.2 Instruction Guide269................................................................................................................................................................
A.3 Notation270................................................................................................................................................................
A-1 Instruction Description Notation271................................................................................................................................................................
A.4 Addressing Modes276................................................................................................................................................................
A-2 Dsp56k Addressing Modes277................................................................................................................................................................
A-3 Dsp56k Addressing Mode Encoding278................................................................................................................................................................
A-4 Addressing Mode Modifier Summary280................................................................................................................................................................
A.5 Condition Code Computation281................................................................................................................................................................
A-5 Condition Code Computations For Instructions (no Parallel Move)285................................................................................................................................................................
A.6 Parallel Move Descriptions286................................................................................................................................................................
A.7 Instruction Descriptions287................................................................................................................................................................
A.8 Instruction Timing560................................................................................................................................................................
A-6 Instruction Timing Summary567................................................................................................................................................................
A-7 Parallel Data Move Timing568................................................................................................................................................................
A-8 Movec Timing Summary568................................................................................................................................................................
A-9 Movep Timing Summary568................................................................................................................................................................
A-10 Bit Manipulation Timing Summary569................................................................................................................................................................
A-11 Jump Instruction Timing Summary569................................................................................................................................................................
A-12 Rti/rts Timing Summary570................................................................................................................................................................
A-13 Addressing Mode Timing Summary570................................................................................................................................................................
A.9 Instruction Sequence Restrictions571................................................................................................................................................................
A-14 Memory Access Timing Summary571................................................................................................................................................................
A.10 Instruction Encoding577................................................................................................................................................................
A-15 Single-bit Register Encodings578................................................................................................................................................................
A-16 Single-bit Special Register Encodings578................................................................................................................................................................
A-17 Double-bit Register Encodings578................................................................................................................................................................
A-18 Triple-bit Register Encodings579................................................................................................................................................................
A-19 (a)four-bit Register Encodings For 12 Registers In Data Alu579................................................................................................................................................................
A-19 (b)four-bit Register Encodings For 16 Condition Codes579................................................................................................................................................................
Data Alu And Address Alu580................................................................................................................................................................
A-21 Six-bit Register Encodings For 43 Registers On-chip580................................................................................................................................................................
A-22 Write Control Encoding580................................................................................................................................................................
A-23 Memory Space Bit Encoding580................................................................................................................................................................
A-25 Condition Code And Address Encoding581................................................................................................................................................................
B.1 Introduction607................................................................................................................................................................
B.2 Benchmark Programs607................................................................................................................................................................
B-1 27-mhz Benchmark Results For The Dsp56001r27608................................................................................................................................................................
B-1 20-tap Fir Filter Example610................................................................................................................................................................
B-2 Radix 2, In-place, Decimation-in-time Fft614................................................................................................................................................................
B-5 Real Input Fft Based On Glenn Bergland Algorithm616................................................................................................................................................................

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Motorola DSP56000 Manual

Motorola DSP56000 Manual (596 pages)

24-BIT  
Brand: Motorola | Category: Processor | Size: 3.37 MB
Table of contents
Table Of Contents6................................................................................................................................................................
Introduction17................................................................................................................................................................
Origin Of Digital Signal Processing17................................................................................................................................................................
Analog Signal Processing18................................................................................................................................................................
Digital Signal Processing19................................................................................................................................................................
Summary Of Dsp56k Family Features24................................................................................................................................................................
Dsp Hardware Origins24................................................................................................................................................................
Manual Organization26................................................................................................................................................................
Dsp56k Central Architecture Overview28................................................................................................................................................................
Data Buses29................................................................................................................................................................
Address Buses29................................................................................................................................................................
Data Alu30................................................................................................................................................................
Address Generation Unit30................................................................................................................................................................
Program Control Unit30................................................................................................................................................................
Memory Expansion Port (port A)33................................................................................................................................................................
On-chip Emulator (once)33................................................................................................................................................................
Phase-locked Loop (pll) Based Clocking33................................................................................................................................................................
Data Arithmetic Logic Unit36................................................................................................................................................................
Overview And Data Alu Architecture36................................................................................................................................................................
Dsp56k Block Diagram37................................................................................................................................................................
Mac Unit40................................................................................................................................................................
Data Alu Accumulator Registers41................................................................................................................................................................
Data Representation And Rounding43................................................................................................................................................................
Saturation Arithmetic43................................................................................................................................................................
Integer-to-fractional Data Conversion44................................................................................................................................................................
Limited Data Values44................................................................................................................................................................
Bit Weighting And Alignment Of Operands45................................................................................................................................................................
Integer/fractional Number Comparison46................................................................................................................................................................
Integer/fractional Multiplication Comparison47................................................................................................................................................................
Convergent Rounding48................................................................................................................................................................
Double Precision Multiply Mode49................................................................................................................................................................
Full Double Precision Multiply Algorithm49................................................................................................................................................................
Data Alu Programming Model52................................................................................................................................................................
Data Alu Summary52................................................................................................................................................................
Dsp56k Programming Model52................................................................................................................................................................
Address Generation Unit And Addressing Modes56................................................................................................................................................................
Agu Architecture56................................................................................................................................................................
Agu Block Diagram58................................................................................................................................................................
Programming Model59................................................................................................................................................................
Agu Programming Model60................................................................................................................................................................
Addressing61................................................................................................................................................................
Address Register Indirect Summary61................................................................................................................................................................
Address Register Indirect — No Update63................................................................................................................................................................
Address Register Indirect — Postincrement64................................................................................................................................................................
Address Register Indirect — Postdecrement65................................................................................................................................................................
Address Register Indirect — Postincrement By Offset Nn66................................................................................................................................................................
Address Register Indirect — Postdecrement By Offset Nn67................................................................................................................................................................
Address Register Indirect — Indexed By Offset Nn68................................................................................................................................................................
Address Register Indirect — Predecrement69................................................................................................................................................................
Address Modifier Summary71................................................................................................................................................................
Circular Buffer72................................................................................................................................................................
Linear Addressing With A Modulo Modifier73................................................................................................................................................................
Modulo Modifier Example74................................................................................................................................................................
Bit-reverse Addressing Sequence Example76................................................................................................................................................................
Bit-reverse Address Calculation Example77................................................................................................................................................................
Overview82................................................................................................................................................................
Program Address Generator82................................................................................................................................................................
Program Control Unit (pcu) Architecture84................................................................................................................................................................
Three-stage Pipeline86................................................................................................................................................................
Program Control Unit Programming Model87................................................................................................................................................................
Status Register Format88................................................................................................................................................................
Omr Format93................................................................................................................................................................
Stack Pointer Register Format94................................................................................................................................................................
Sp Register Values95................................................................................................................................................................
Dsp56k Central Processing Module Programming Model97................................................................................................................................................................
Instruction Set Introduction100................................................................................................................................................................
Syntax100................................................................................................................................................................
Instruction Formats100................................................................................................................................................................
General Format Of An Instruction Operation Word102................................................................................................................................................................
Operand Sizes103................................................................................................................................................................
Reading And Writing The Alu Extension Registers104................................................................................................................................................................
Reading And Writing The Address Alu Registers104................................................................................................................................................................
Reading And Writing Control Registers105................................................................................................................................................................
Special Addressing – Immediate Data113................................................................................................................................................................
Special Addressing – Absolute Addressing114................................................................................................................................................................
Special Addressing – Short Jump Address116................................................................................................................................................................
Instruction Groups117................................................................................................................................................................
Special Addressing – Absolute Short Address117................................................................................................................................................................
Special Addressing – I/o Short Address118................................................................................................................................................................
Hardware Do Loop122................................................................................................................................................................
Nested Do Loops124................................................................................................................................................................
Classifications Of Parallel Data Moves124................................................................................................................................................................
Parallel Move Examples125................................................................................................................................................................
Processing States128................................................................................................................................................................
Normal Processing State130................................................................................................................................................................
Instruction Pipelining130................................................................................................................................................................
Exception Processing State (interrupt Processing)137................................................................................................................................................................
Fast And Long Interrupt Examples140................................................................................................................................................................
Interrupt Priority Register (addr X:$ffff)141................................................................................................................................................................
Status Register Interrupt Mask Bits141................................................................................................................................................................
Interrupt Priority Level Bits142................................................................................................................................................................
External Interrupt142................................................................................................................................................................
Central Processor Interrupt Priorities Within An Ipl142................................................................................................................................................................
Interrupt Sources143................................................................................................................................................................
Interrupting An Swi144................................................................................................................................................................
Illegal Instruction Interrupt Serviced By A Fast Interrupt146................................................................................................................................................................
Illegal Instruction Interrupt Serviced By A Long Interrupt147................................................................................................................................................................
Repeated Illegal Instruction148................................................................................................................................................................
Trace Exception150................................................................................................................................................................
Fast Interrupt Service Routine154................................................................................................................................................................
Two Consecutive Fast Interrupts155................................................................................................................................................................
Long Interrupt Service Routine157................................................................................................................................................................
Jsr First Instruction Of A Fast Interrupt158................................................................................................................................................................
Jsr Second Instruction Of A Fast Interrupt159................................................................................................................................................................
Reset Processing State160................................................................................................................................................................
Interrupting An Rep Instruction161................................................................................................................................................................
Interrupting Sequential Rep Instructions162................................................................................................................................................................
Wait Processing State163................................................................................................................................................................
Wait Instruction Timing163................................................................................................................................................................
Stop Processing State164................................................................................................................................................................
Simultaneous Wait Instruction And Interrupt164................................................................................................................................................................
Stop Instruction Sequence165................................................................................................................................................................
Stop Instruction Sequence Followed By Irqa166................................................................................................................................................................
Stop Instruction Sequence Recovering With Reset169................................................................................................................................................................
Port A Overview173................................................................................................................................................................
Port A Interface173................................................................................................................................................................
Port A Signals174................................................................................................................................................................
Pll Clock Oscillator Introduction181................................................................................................................................................................
Pll Components181................................................................................................................................................................
Pll Control Register (pctl)184................................................................................................................................................................
Multiplication Factor Bits Mf0-mf11184................................................................................................................................................................
Division Factor Bits Df0-df3185................................................................................................................................................................
Pstp And Pen Relationship187................................................................................................................................................................
Clock Output Disable Bits Cod0-cod1187................................................................................................................................................................
Pll Pins188................................................................................................................................................................
Pll Operation Considerations190................................................................................................................................................................
On-chip Emulation Introduction196................................................................................................................................................................
On-chip Emulation (once) Pins196................................................................................................................................................................
Once Block Diagram196................................................................................................................................................................
Chip Status Information198................................................................................................................................................................
Once Controller And Serial Interface199................................................................................................................................................................
Once Command Register200................................................................................................................................................................
Once Register Addressing200................................................................................................................................................................
Once Status And Control Register (oscr)202................................................................................................................................................................
Memory Breakpoint Control Table203................................................................................................................................................................
Once Memory Breakpoint Logic204................................................................................................................................................................
Once Trace Logic206................................................................................................................................................................
Once Trace Logic Block Diagram207................................................................................................................................................................
Methods Of Entering The Debug Mode208................................................................................................................................................................
Pipeline Information And Global Data Bus Register209................................................................................................................................................................
Once Pipeline Information And Gdb Registers210................................................................................................................................................................
Program Address Bus History Buffer211................................................................................................................................................................
Once Pab Fifo211................................................................................................................................................................
Serial Protocol Description212................................................................................................................................................................
Dsp56k Target Site Debug System Requirements213................................................................................................................................................................
Using The Once213................................................................................................................................................................
User Support224................................................................................................................................................................
Motorola Dsp Product Support225................................................................................................................................................................
Dsp56kadsx Application Development System227................................................................................................................................................................
Dr. Bub Electronic Bulletin Board228................................................................................................................................................................
Motorola Dsp News237................................................................................................................................................................
Motorola Field Application Engineers237................................................................................................................................................................
Design Hotline– 1-800-521-6274237................................................................................................................................................................
Dsp Help Line – (512) 891-3230237................................................................................................................................................................
Marketing Information– (512) 891-2030237................................................................................................................................................................
Third-party Support Information – (512) 891-3098237................................................................................................................................................................
University Support – (512) 891-3098237................................................................................................................................................................
Training Courses – (602) 897-3665 Or (800) 521-6274238................................................................................................................................................................
Reference Books And Manuals238................................................................................................................................................................
A.1 Appendix A Introduction271................................................................................................................................................................
A.2 Instruction Guide271................................................................................................................................................................
A.3 Notation273................................................................................................................................................................
A.4 Addressing Modes279................................................................................................................................................................
A.5 Condition Code Computation284................................................................................................................................................................
A.6 Parallel Move Descriptions289................................................................................................................................................................
A.7 Instruction Descriptions290................................................................................................................................................................
B.1 Introduction565................................................................................................................................................................
B.2 Benchmark Programs565................................................................................................................................................................
B-1 27-mhz Benchmark Results For The Dsp56001r27566................................................................................................................................................................
B-1 20-tap Fir Filter Example568................................................................................................................................................................
B-2 Radix 2, In-place, Decimation-in-time Fft572................................................................................................................................................................
B-5 Real Input Fft Based On Glenn Bergland Algorithm574................................................................................................................................................................

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