INTEL 6 SERIES CHIPSET - UPDATE 01-2011 Manuals

Manuals and User Guides for INTEL 6 SERIES CHIPSET - UPDATE 01-2011. We have 2 INTEL 6 SERIES CHIPSET - UPDATE 01-2011 manuals available for free PDF download: Datasheet, Specification

INTEL 6 SERIES CHIPSET - UPDATE 01-2011 Datasheet

INTEL 6 SERIES CHIPSET - UPDATE 01-2011 Datasheet (936 pages)

Brand: INTEL | Category: Controller | Size: 5.19 MB

Table of Contents

Table of Contents

3
Figures

32
- 1 Introduction
  
  41
  - About this Manual
    41
  - Industry Specifications
    41
  - Overview
    44
    
    Capability Overview
    45
  - Intel ® 6 Series Chipset SKU Definition
    51
  - Desktop Intel
    51
    
    Series Chipset Skus
    51
  - Mobile Intel
    52
    
    Series Chipset Skus
    52
- 2 Signal Description
  
  53
  - PCH Interface Signals Block Diagram (Not All Signals Are on All Skus)
    54
    
    Direct Media Interface (DMI) to Host Controller
    55
    
    Direct Media Interface Signals
    55
    
    PCI Express
    55
    
    PCI Express* Signals
    55
    
    PCI Interface
    56
    
    PCI Interface Signals
    56
    
    Serial ATA Interface
    58
    
    Serial ATA Interface Signals
    58
    
    Interrupt Interface
    61
    
    Interrupt Signals
    61
    
    LPC Interface
    61
    
    LPC Interface Signals
    61
    
    USB Interface
    62
    
    USB Interface Signals
    62
    
    Power Management Interface
    63
    
    Power Management Interface Signals
    63
    
    Processor Interface
    67
    
    Processor Interface Signals
    67
    
    SM Bus Interface Signals
    67
    
    Smbus Interface
    67
    
    Real Time Clock Interface
    68
    
    System Management Interface
    68
    
    System Management Interface Signals
    68
    
    Miscellaneous Signals
    69
    
    High Definition Audio Link
    70
    
    High Definition Audio Link Signals
    70
    
    Intel
    70
    
    Controller Link
    71
    
    Controller Link Signals
    71
    
    Serial Peripheral Interface (SPI)
    71
    
    Serial Peripheral Interface (SPI) Signals
    71
    
    Thermal Signals
    71
    
    Clock Interface Signals
    72
    
    Clock Signals
    72
    
    Testability Signals
    72
    
    LVDS Interface Signals
    74
    
    LVDS Signals
    74
    
    Analog Display /VGA DAC Signals
    75
    
    Analog Display Interface Signals
    75
    
    Flexible Display Interface (Intel ® FDI)
    76
    
    Flexible Display Interface Signals
    76
    
    Intel
    76
    
    Digital Display Interface Signals
    77
    
    Digital Display Signals
    77
    
    General Purpose I/O Signals
    80
    
    Manageability Signals
    84
    
    Power and Ground Signals
    85
    
    Functional Strap Definitions
    87
    
    Pin Straps
    87
    
    Example External RTC Circuit
    91
    
    External RTC Circuitry
    91
- 3 PCH Pin States
  
  93
- 4 PCH and System Clocks
  
  113
  - Platform Clocking Requirements
    113
  - PCH Clock Inputs
    113
  - Clock Outputs
    114
    
    Functional Blocks
    115
    
    PCH Plls
    115
    
    Clock Configuration Access Overview
    116
    
    SSC Blocks
    116
    
    Straps Related to Clock Configuration
    116
- 5 Functional Description
  
  117
  - DMI-To-PCI Bridge (D30:F0)
    117
    
    PCI Legacy Mode
    117
  - PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7)
    118
    
    Interrupt Generation
    118
  - MSI Versus PCI IRQ Actions
    118
    
    Device Initiated PM_PME Message
    119
    
    Power Management
    119
    
    Resuming from Suspended State
    119
    
    S3/S4/S5 Support
    119
    
    Hot-Plug
    120
    
    SERR# Generation
    120
    
    SMI/SCI Generation
    120
  - Generation of SERR# to Platform
    120
    
    Attention Button Detection
    121
    
    Message Generation
    121
    
    Presence Detection
    121
  - Gigabit Ethernet Controller (B0:D25:F0)
    122
    
    SMI/SCI Generation
    122
    
    Configuration Request Retry Status
    124
    
    Data Alignment
    124
    
    Data Parity Error
    124
    
    Error Events and Error Reporting
    124
    
    Gbe PCI Express* Bus Interface
    124
    
    Transaction Layer
    124
    
    82579 LAN PHY Interface
    125
    
    Completion with Unsuccessful Completion Status
    125
    
    Ethernet Interface
    125
    
    LAN Mode Support
    125
    
    PCI Power Management
    125
    
    Wake up
    126
    
    Configurable Leds
    127
    
    FLR Steps
    128
    
    Function Level Reset Support (FLR)
    128
  - LPC Bridge (with System and Management Functions) (D31:F0)
    129
    
    LPC Interface
    129
    
    LPC Interface Diagram
    129
    
    LPC Cycle Types
    130
    
    LPC Cycle Types Supported
    130
    
    Start Field Bit Definitions
    130
    
    Start Field Definition
    130
    
    Cycle Type / Direction (CYCTYPE + DIR)
    131
    
    Cycle Type Bit Definitions
    131
    
    Size
    131
    
    Transfer Size Bit Definition
    131
    
    LFRAME# Usage
    132
    
    Sync
    132
    
    SYNC Bit Definition
    132
    
    SYNC Error Indication
    132
    
    SYNC Time-Out
    132
    
    Bus Master Cycles
    133
    
    Configuration and PCH Implications
    133
    
    I/O Cycles
    133
    
    LPC Power Management
    133
  - DMA Operation (D31:F0)
    134
    
    Channel Priority
    134
    
    Fixed Priority
    134
    
    PCH DMA Controller
    134
    
    Address Compatibility Mode
    135
    
    DMA Transfer Size
    135
    
    Rotating Priority
    135
    
    Summary of DMA Transfer Sizes
    135
    
    Address Shifting in 16-Bit I/O DMA Transfers
    136
    
    Autoinitialize
    136
    
    Software Commands
    136
  - Lpc Dma
    137
    
    Abandoning DMA Requests
    137
    
    Asserting DMA Requests
    137
    
    DMA Request Assertion through LDRQ
    137
    
    General Flow of DMA Transfers
    138
    
    Terminal Count
    138
    
    Verify Mode
    138
    
    DMA Request Deassertion
    139
    
    SYNC Field / LDRQ# Rules
    139
  - 8254 Timers (D31:F0)
    140
    
    Counter Operating Modes
    141
    
    Timer Programming
    141
    
    Counter Latch Command
    142
    
    Read Back Command
    142
    
    Reading from the Interval Timer
    142
    
    Simple Read
    142
  - 8259 Interrupt Controllers (PIC) (D31:F0)
    143
    
    Interrupt Controller Core Connections
    143
    
    Acknowledging Interrupts
    144
    
    Content of Interrupt Vector Byte
    144
    
    Generating Interrupts
    144
    
    Interrupt Handling
    144
    
    Interrupt Status Registers
    144
    
    Hardware/Software Interrupt Sequence
    145
    
    Icw1
    145
    
    Initialization Command Words (Icwx)
    145
    
    Fully Nested Mode
    146
    
    Icw2
    146
    
    Icw3
    146
    
    Icw4
    146
    
    Modes of Operation
    146
    
    Operation Command Words (OCW)
    146
    
    Automatic Rotation Mode (Equal Priority Devices)
    147
    
    Poll Mode
    147
    
    Special Fully-Nested Mode
    147
    
    Automatic End of Interrupt Mode
    148
    
    Cascade Mode
    148
    
    Edge and Level Triggered Mode
    148
    
    End of Interrupt (EOI) Operations
    148
    
    Normal End of Interrupt
    148
    
    Masking Interrupts
    149
    
    Masking on an Individual Interrupt Request
    149
    
    Special Mask Mode
    149
    
    Steering PCI Interrupts
    149
    
    Advanced Programmable Interrupt Controller (APIC) (D31:F0)
    150
    
    APIC Interrupt Mapping1
    150
    
    Interrupt Handling
    150
    
    Interrupt Mapping
    150
    
    External Interrupt Controller Support
    151
    
    Ioxapic Address Remapping
    151
    
    PCI / PCI Express* Message-Based Interrupts
    151
    
    Serial Interrupt (D31:F0)
    152
    
    Start Frame
    152
    
    Data Frames
    153
    
    Specific Interrupts Not Supported Using SERIRQ
    153
    
    Stop Frame
    153
    
    Stop Frame Explanation
    153
    
    Data Frame Format
    154
    
    Real Time Clock (D31:F0)
    155
    
    Update Cycles
    155
    
    Century Rollover
    156
    
    Clearing Battery-Backed RTC RAM
    156
    
    Interrupts
    156
    
    Lockable RAM Ranges
    156
  - Configuration Bits Reset by RTCRST# Assertion
    157
    
    A20M# (Mask A20) / A20GATE
    158
    
    Processor Interface (D31:F0)
    158
    
    Processor Interface Signals and VLW Messages
    158
    
    FERR# (Numeric Coprocessor Error)
    159
    
    INIT (Initialization)
    159
    
    INIT# Going Active
    159
    
    Dual-Processor Issues
    160
    
    NMI (Non-Maskable Interrupt)
    160
    
    NMI Sources
    160
    
    Processor Power Good (PROCPWRGD)
    160
    
    Usage Differences
    160
    
    Virtual Legacy Wire (VLW) Messages
    160
    
    Features
    161
    
    General Power States for Systems Using the PCH
    161
    
    PCH and System Power States
    161
    
    Power Management
    161
  - State Transition Rules for the PCH
    162
    
    SMI#/SCI Generation
    163
    
    System Power Plane
    163
    
    System Power Planes
    163
  - Causes of SMI and SCI
    164
    
    PCI Express* Hot-Plug
    165
    
    PCI Express* SCI
    165
    
    C-States
    166
    
    Conditions for Checking the PCI Clock
    166
    
    Conditions for Maintaining the PCI Clock
    166
    
    Conditions for Stopping the PCI Clock
    166
    
    Dynamic PCI Clock Control (Mobile Only)
    166
    
    Conditions for Re-Starting the PCI Clock
    167
    
    Initiating Sleep State
    167
    
    LPC Devices and CLKRUN
    167
    
    Sleep State Overview
    167
    
    Sleep States
    167
    
    Causes of Wake Events
    168
    
    Exiting Sleep States
    168
    
    Sleep Types
    168
    
    GPI Wake Events
    170
    
    PCI Express* WAKE# Signal and PME Event Message
    170
    
    Sx-G3-Sx, Handling Power Failures
    170
    
    Deep S4/S5
    171
    
    Supported Deep S4/S5 Policy Configurations
    171
    
    Transitions Due to Power Failure
    171
    
    Deep S4/S5 Wake Events
    172
    
    Event Input Signals and Their Usage
    172
    
    PWRBTN# (Power Button)
    172
  - Transitions Due to Power Button
    173
    
    PME# (PCI Power Management Event)
    174
    
    RI# (Ring Indicator)
    174
    
    SYS_RESET# Signal
    174
    
    THRMTRIP# Signal
    174
    
    Transitions Due to RI# Signal
    174
    
    ALT Access Mode
    175
    
    Write Only Registers with Read Paths in ALT Access Mode
    176
    
    10System Power Supplies, Planes, and Signals
    178
    
    PIC Reserved Bits
    178
    
    PIC Reserved Bits Return Values
    178
    
    Read Only Registers with Write Paths in ALT Access Mode
    178
    
    Register Write Accesses in ALT Access Mode
    178
    
    SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN
    178
    
    11Clock Generators
    179
    
    12Legacy Power Management Theory of Operation
    179
    
    1Power Plane Control with SLP_S3#, 5.13.10.2SLP_S4# and Suspend-To-RAM Sequencing
    179
    
    3PWROK Signal
    179
    
    4BATLOW# (Battery Low) (Mobile Only)
    179
    
    13Reset Behavior
    180
    
    1APM Power Management (Desktop Only)
    180
    
    2Mobile APM Power Management (Mobile Only)
    180
  - Causes of Host and Global Resets
    181
  - System Management (D31:F0)
    182
    
    Detecting a System Lockup
    182
    
    Theory of Operation
    182
    
    Detecting Improper Flash Programming
    183
    
    Handling an Intruder
    183
    
    Heartbeat and Event Reporting Using Smlink/Smbus
    183
    
    TCO Legacy/Compatible Mode
    183
    
    TCO Modes
    183
  - TCO Legacy/Compatible Mode Smbus Configuration
    184
  - Event Transitions that Cause Messages
    184
    
    Advanced TCO Mode
    185
  - General Purpose I/O (D31:F0)
    186
    
    GPIO Registers Lockdown
    186
    
    Power Wells
    186
    
    SMI# SCI and NMI Routing
    186
    
    Triggering
    186
    
    Serial POST Codes over GPIO
    187
    
    Serial Post over GPIO Reference Circuit
    187
    
    Theory of Operation
    187
    
    Serial Message Format
    188
  - SATA Host Controller (D31:F2, F5)
    189
    
    Sata
    189
    
    Gb/S Support
    190
    
    SATA Feature Support
    190
    
    48-Bit LBA Operation
    191
    
    Hot Plug Operation
    191
    
    Low Power Device Presence Detection
    191
    
    SATA Swap Bay Support
    191
    
    Standard ATA Emulation
    191
    
    Theory of Operation
    191
    
    FLR Steps
    192
    
    Function Level Reset Support (FLR)
    192
    
    Rapid Storage Technology Configuration
    192
    
    Power Management Operation
    193
    
    Power State Mappings
    193
    
    Rapid Storage Manager RAID Option ROM
    193
    
    Power State Transitions
    194
    
    Flow for Port Enable / Device Present Bits
    195
    
    SATA Device Presence
    195
    
    SMI Trapping (APM)
    195
    
    10Sata Led
    196
    
    11AHCI Operation
    196
    
    12SGPIO Signals
    196
    
    1Mechanism
    196
    
    2Message Format
    197
    
    3LED Message Type
    198
    
    Multi-Activity LED Message Type
    198
    
    4SGPIO Waveform
    199
    
    Serial Data Transmitted over the SGPIO Interface
    199
    
    13External SATA
    200
  - High Precision Event Timers
    200
    
    Timer Accuracy
    200
    
    Interrupt Mapping
    201
    
    Legacy Replacement Routing
    201
    
    Periodic Vs. Non-Periodic Modes
    201
    
    Enabling the Timers
    202
    
    Interrupt Levels
    202
    
    Handling Interrupts
    203
    
    Issues Related to 64-Bit Timers with 32-Bit Processors
    203
  - USB EHCI Host Controllers (D29:F0 and D26:F0)
    204
    
    BIOS Initialization
    204
    
    Data Structures in Main Memory
    204
    
    Driver Initialization
    204
    
    EHC Initialization
    204
    
    EHC Resets
    204
    
    Data Encoding and Bit Stuffing
    205
    
    Packet Formats
    205
    
    USB 2.0 Enhanced Host Controller DMA
    205
    
    USB 2.0 Interrupts and Error Conditions
    205
    
    Aborts on USB 2.0-Initiated Memory Reads
    206
    
    ACPI Device States
    206
    
    Pause Feature
    206
    
    Suspend Feature
    206
    
    USB 2.0 Power Management
    206
    
    ACPI System States
    207
    
    USB 2.0 Based Debug Port
    207
    
    USB 2.0 Legacy Keyboard Operation
    207
    
    Debug Port Behavior
    208
    
    Theory of Operation
    208
    
    10EHCI Caching
    212
    
    12Function Level Reset Support (FLR)
    212
    
    1FLR Steps
    212
    
    USB Pre-Fetch Based Pause
    212
    
    13USB Overcurrent Protection
    213
    
    Architecture
    214
    
    EHCI with USB 2.0 with Rate Matching Hub
    214
    
    Integrated USB 2.0 Rate Matching Hub
    214
    
    Overview
    214
    
    Host Controller
    215
    
    Smbus Controller (D31:F3)
    215
    
    Command Protocols
    216
  - C Block Read
    218
    
    Bus Arbitration
    219
    
    Bus Time out (the PCH as Smbus Master)
    220
    
    Bus Timing
    220
    
    Clock Stretching
    220
    
    Enable for SMBALERT
    220
    
    Interrupts / SMI
    220
    
    Enables for Smbus Slave Write and Smbus Host Events
    221
    
    Enables for the Host Notify Command
    221
    
    Smbalert
    221
    
    Smbus CRC Generation and Checking
    221
    
    Format of Slave Write Cycle
    222
    
    Smbus Slave Interface
    222
  - Slave Write Registers
    223
  - Command Types
    223
    
    Format of Read Command
    224
    
    Slave Read Cycle Format
    224
  - Data Values for Slave Read Registers
    225
    
    Slave Read of RTC Time Bytes
    226
    
    Format of Host Notify Command
    227
    
    Host Notify Format
    227
    
    Internal Thermal Sensor Operation
    228
    
    Thermal Management
    228
    
    Thermal Sensor
    228
    
    Thermal Reporting over System Management Link 1 Interface (Smlink1)
    229
    
    Supported Addresses
    230
    
    Block Read Command
    231
    
    C Write Commands to the Intel ME
    231
    
    Ime
    231
  - Block Read Command - Byte Definition
    232
    
    Read Data Format
    233
    
    Temperature Comparator and Alert
    233
    
    Thermal Data Update Rate
    233
    
    BIOS Set up
    235
    
    Smbus Rules
    235
    
    Case for Considerations
    236
    
    Dock Sequence
    238
    
    High Definition Audio Docking (Mobile Only)
    238
    
    High Definition Audio Overview (D27:F0)
    238
    
    Exiting D3/CRST# When Docked
    239
    
    Cold Boot/Resume from S3 When Docked
    240
    
    Normal Undock
    240
    
    Undock Sequence
    240
    
    Interaction between Dock/Undock and Power Management States
    241
    
    Relationship between HDA_DOCK_RST# and HDA_RST
    241
    
    Surprise Undock
    241
    
    ME Firmware 7.0
    242
    
    Serial Peripheral Interface (SPI)
    242
    
    SPI Supported Feature Overview
    242
  - Region Size Versus Erase Granularity of Flash Components
    244
  - Flash Descriptor Sections
    245
  - Region Access Control Table
    246
  - Hardware Sequencing Commands and Opcode Requirements
    249
  - Flash Protection Mechanism Summary
    251
  - Recommended Pinout for 8-Pin Serial Flash Device
    252
  - Recommended Pinout for 16-Pin Serial Flash Device
    252
  - Analog Port Characteristics
    254
  - LVDS Signals and Swing Voltage
    256
  - LVDS Clock and Data Relationship
    256
  - Panel Power Sequencing
    257
  - HDMI Overview
    258
  - DP Overview
    259
  - PCH Supported Audio Formats over HDMI and Displayport
    260
  - SDVO Conceptual Block Diagram
    261
  - PCH Digital Port Pin Mapping
    262
  - Display Co-Existence Table
    263
  - Virtualization Support for High Precision Event Timer (HPET)
    265
  - Desktop PCH Ballout (Top View - Upper Left)
    268
  - Desktop PCH Ballout (Top View - Lower Left)
    269
  - Desktop PCH Ballout (Top View - Upper Right)
    270
  - Desktop PCH Ballout (Top View - Lower Right)
    271
  - Desktop PCH Ballout by Signal Name
    272
  - Mobile PCH Ballout (Top View - Upper Left)
    280
  - Mobile PCH Ballout (Top View - Lower Left)
    281
  - Mobile PCH Ballout (Top View - Upper Right)
    282
  - Mobile PCH Ballout (Top View - Lower Right)
    283
  - Mobile PCH Ballout by Signal Name
    284
  - Desktop PCH Package Drawing
    294
  - Mobile PCH Package Drawing
    296
  - Storage Conditions
    297
  - Mobile Thermal Design Power
    298
  - PCH Absolute Maximum Ratings
    298
  - PCH Power Supply Range
    299
    
    (Desktop Only)
    299
    
    (Mobile Only)
    300
  - DC Characteristic Input Signal Association
    302
  - DC Input Characteristics
    304
  - DC Characteristic Output Signal Association
    307
  - DC Output Characteristics
    309
  - Other DC Characteristics
    311
  - Signal Groups
    312
  - CRT DAC Signal Group DC Characteristics: Functional Operating Range
    312
    
    (Vccadac = 3.3 V ±5%)
    312
  - LVDS Interface: Functional Operating Range (Vccalvds = 1.8 V ±5%)
    313
  - Display Port Auxiliary Signal Group DC Characteristics
    313
  - PCI Express* Interface Timings
    314
  - HDMI Interface Timings (Ddp[D:b][3:0])Timings
    315
  - SDVO Interface Timings
    315
  - Displayport Interface Timings (DDP[D:B][3:0])
    316
  - Displayport aux Interface
    317
  - DDC Characteristics
    317
  - LVDS Interface AC Characteristics at Various Frequencies
    318
  - CRT DAC AC Characteristics
    320
  - Clock Timings
    320
  - PCI Interface Timing
    324
  - Universal Serial Bus Timing
    325
  - SATA Interface Timings
    326
  - Smbus and Smlink Timing
    327
  - LPC Timing
    328
  - Miscellaneous Timings
    328
    
    High Definition Audio Timing
    328
  - SPI Timings (20 Mhz)
    329
  - SPI Timings (33 Mhz)
    329
  - SPI Timings (50 Mhz)
    330
  - Controller Link Receive Timings
    330
  - Power Sequencing and Reset Signal Timings
    331
  - G3 W/Rtc Loss to S4/S5 (with Deep S4/S5 Support) Timing Diagram
    334
  - G3 W/Rtc Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram
    334
  - S5 to S0 Timing Diagram
    335
  - S3/M3 to S0 Timing Diagram
    336
  - S5/Moff - S5/M3 Timing Diagram
    336
  - S0 to S5 Timing Diagram
    337
  - S4/S5 to Deep S4/S5 to G3 W/ RTC Loss Timing Diagram
    338
  - DRAMPWROK Timing Diagram
    338
  - Clock Cycle Time
    339
  - Transmitting Position (Data to Strobe)
    339
  - Clock Timing
    339
  - Setup and Hold Times
    340
  - Float Delay
    340
  - Pulse Width
    340
  - Valid Delay from Rising Clock Edge
    340
  - Output Enable Delay
    341
  - USB Rise and Fall Times
    341
  - USB Jitter
    341
  - USB EOP Width
    342
  - Smbus Transaction
    342
  - Smbus Timeout
    342
  - SPI Timings
    343
    
    High Definition Audio Input and Output Timings
    343
  - Dual Channel Interface Timings
    344
  - LVDS Load and Transition Times
    344
  - Transmitting Position (Data to Strobe)
    345
  - PCI Express Transmitter Eye
    345
  - PCI Express Receiver Eye
    346
  - Measurement Points for Differential Waveforms
    347
  - PCH Test Load
    348
  - Controller Link Receive Timings
    348
  - Controller Link Receive Slew Rate
    348
  - PCI Devices and Functions
    350
    
    Address Map
    351
  - Fixed I/O Ranges Decoded by Intel
    352
    
    Pch
    352
  - Variable I/O Decode Ranges
    354
  - Memory Decode Ranges from Processor Perspective
    355
  - Chipset Configuration Register Memory Map (Memory Space)
    359
  - PCI Bridge Register Address Map (PCI-PCI-D30:F0)
    415
  - Gigabit LAN Configuration Registers Address Map
    433
    
    (Gigabit LAN -D25:F0)
    433
  - LPC Interface PCI Register Address Map (LPC I/F-D31:F0)
    447
    
    LPC Interface Bridge Registers (D31:F0)
    447
  - DMA Registers
    474
  - PIC Registers
    485
  - APIC Direct Registers
    493
  - APIC Indirect Registers
    493
  - RTC I/O Registers
    498
  - RTC (Standard) RAM Bank
    499
  - Processor Interface PCI Register Address Map
    503
  - Power Management PCI Register Address Map (PM-D31:F0)
    506
  - APM Register Map
    515
  - ACPI and Legacy I/O Register Map
    516
  - TCO I/O Register Address Map
    534
  - Registers to Control GPIO Address Map
    541
  - SATA Controller PCI Register Address Map (SATA-D31:F2)
    551
    
    When Sub Class Code Register (D31:F2:Offset 0Ah) = 01H
    555
  - Bus Master IDE I/O Register Address Map
    579
  - AHCI Register Address Map
    588
  - Generic Host Controller Register Address Map
    589
  - Port [5:0] DMA Register Address Map
    599
  - SATA Controller PCI Register Address Map (SATA-D31:F5)
    617
  - Bus Master IDE I/O Register Address Map
    633
  - USB EHCI PCI Register Address Map (USB EHCI-D29:F0, D26:F0)
    641
  - Enhanced Host Controller Capability Registers
    661
  - Enhanced Host Controller Operational Register Address Map
    664
  - Debug Port Register Address Map
    678
    
    High Definition Audio D27:F0)
    683
    
    High Definition Audio PCI Register Address Map
    683
    
    High Definition Audio D27:F0)
    706
    
    High Definition Audio Memory Mapped Configuration Registers
    706
  - Configuration Default
    733
  - Configuration Data Structure
    733
  - Port Connectivity
    735
  - Location
    735
  - Default Device
    736
  - Connection Type
    736
  - Misc
    737
  - Color
    737
  - Smbus Controller PCI Register Address Map (Smbus-D31:F3)
    739
  - Smbus I/O and Memory Mapped I/O Register Address Map
    746
  - PCI Express* Configuration Registers Address Map
    757
    
    (PCI Express*-D28:F0/F1/F2/F3/F4/F5/F6/F7)
    757
  - Memory-Mapped Registers
    799
  - Serial Peripheral Interface (SPI) Register Address Map
    809
    
    (SPI Memory Mapped Configuration Registers)
    809
  - Gigabit LAN SPI Flash Program Register Address Map
    832
    
    (Gbe LAN Memory Mapped Configuration Registers)
    832
  - Thermal Sensor Register Address Map
    845
  - Thermal Memory Mapped Configuration Register Address Map
    854
  - Intel (MEI - D22:F0)
    867
    
    MEI Configuration Registers Address Map
    867
  - MEI1 Configuration Registers Address Map
    879
    
    (Mei -D22:F1)
    879
  - MEI MMIO Register Address Map (VE - D23:F0)
    888
  - MEI MMIO Register Address Map (VE - D23:F0)
    891
  - IDE Function for Remote Boot and Installations PT IDER Register Address Map
    894

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INTEL 6 SERIES CHIPSET - UPDATE 01-2011 Specification

INTEL 6 SERIES CHIPSET - UPDATE 01-2011 Specification (20 pages)

chipset

Brand: INTEL | Category: Controller | Size: 0.11 MB

Table of Contents

Table of Contents
3
Preface
5
Summary Tables of Changes
6
Identification Information
8
PCH Device and Revision Identification
9
Errata
12
Specification Changes
17
Specification Clarification
18
Documentation Changes
19

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