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Ic Block Diagram - Sanyo MCD-ZI00F Service Manual

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IC BLOCK DIAGRAM
& DESCRIPTION
.
IC5 LC78622E(Digital
Signal
Processor)
No.
Name
1/0
Function
1
DEFI
I
Input
of defect
detection
signal.
( Not
used : Connect to OV)
2
TAU
I
For
PLL.
Input
for test.
(Surely
connect
to OV)
3
PDO
o
For PLL. Outputof phasecomparator f orexternalVCO.
4
Vvss
-
For PLL. Ground for internal VCO. (Surely connect to OV)
5
ISET
Al
For PLL. Connection of resistor for current adjustment of
PDO output.
6
WDD
-
For PLL. Power supply for internal VCO.
7
m
Al
For PLL. For adjustment of VCO frequency range.
8
Vss
-
Ground for digital root. (Surely connect to OV)
9
EFMO
o
Output of EFM signal for slice level control.
10
EFMIN
I
Input of EFM signal for slice level control.
11
TEST2
I
Input for test. (Surely connect to OV)
12
CLV+
o
Output for disc motor control.
13
CLV-
0
Output for disc motor control.
14
v ~:
o
Monitor output for automatic selection of rough servolphase
control.
H : rough servo, 'b: phase control
15
HFL
I
Input of track detection signal.
16
TES
I
Input of tracking error signal.
17
TOFF
o
Ou!put of trackima OFF signal.
18
TGL
o
Output of selection for tracking gain. "~ level : gain up
19
JP+
o
Output of track jump control.
20
JP-
0
Output of track jump control.
21
PCK
o
Output of clock monitor for playback EFM data.
When rocked the phase : 4.3218MHz
22
FSEQ
o
Output of detection for synchronizing signal.
When accordant to detected synchronizing signal from
EFM signaf and synchronizing signal in internal generation.
23
VDD
-
Power supply for digital root.
24
CONT1
1/0
25
CONT2
1/0 Inpuf/Output for general.
26
CONT3
1/0 Control by serial data command from
micro
processor.
27
CONT4
1/0 Not used Open or OV
28
CONT5
1/0
29
EMPH
o
Output of monitor for de-emphasis.
Playback during diemphasis disc: 'W level
30
C2F
o
Output of
C2
flag.
31
DOUT
o
Output of Digital OUT. (EIAJ foamed)
32
TEST3
II
nput for test. (Surely connect to OV)
33
TEST4
II
nput for test. (Surely connect to OV)
34
w
-
Not connection. (Open)
qol
Name~/d
Function
35 I MUTEL I O ] L-channel l-bit DAC. Output of muting for L-channel.
I
36
LVDD
-
L-channel l-bit DAC. Power supply for L-channel.
37
LCHO
o
L-channel 1-bit DAC. Output signal for L-channel.
38
LVSS
-
L-channel l-bit DAC. Ground terminal for L-channel.
(Surely connect to OV)
39
RVSS
-
R-channel l-bit DAC. Ground terminal for R-channel.
(Surely connect to OV)
40
RCHO
o
R-channel 1-bit DAC. Output signal for R-channel.
41
RVDD
-
R-channel
l-bit
DAC. Power supply for R-channel.
42 MUTER
o
R-channel l-bit DAC. Output of muting for R-channel.
43
XVDD
-
Power supply terminal for crystal oscillation.
44
XOUT
o
Connection terminal for crystal oscillation. (16.9344MHz~
45
XIN
I
Connection terminal for crystal oscillation. (16.9345MHz~
46
Xvss
o
Ground terminal for crystal oscillation.
I
I
I (Surely connect to OV)
47 I SBSY ] O 10utput of Synchronizing signal for sub-code block.
I
48 I EFLG I O lTerminal of correction monitor for Cl, C2, single
I
I
I
I and
double.
491
F-W
I O 10utput for P, Q, R, S, T, U and W of sub-code.
I
50 I SFSY I O 10utput of Synchronizing signal for sub-code flame.
I
When the stand-by the sub-code, leading edge.
51
SBCK
I
Input terminal of reading clock for sub-code.
52
FSX
o
Output terminal of synchronizing signa! divided from
crystal oscillation (7.35 kHz).
53
WFtQ
o Output of stand-by signal for output the sub-code Q.
54
M
I
Input terminal of control signal for readlwrite.
55 SQOUT
o
Output terminal for sub-code Q.
56
COIN
I
Input terminal for command from micro-processor.
57
CQCK
I
Input of loading clock for command, or fetching clock for
sub-code from SQOUT.
58
E
f
Input te~inal
of system reset. When ON the power
supply, ones the 'L".
S9 TST11
o
Output terminal for test.
-
--
-
Use the Ope n status(Normal the output is "L").
$0
16M
o Output terminal for 16.9344MHz.
~
52 TEST5
I
In ut for test. Surel connect to OV
I
in ut terminal for chi select si nal
When the un-control, connect to OV
}4 TEST1
I
In ut for test. Surel connect to OV
EFMD
1S111 TEST2 1SS14
WDD
VVSS
Pm
ISET FR
PCK
'a,
7==7.
7=.,.
7==.=
'm
'i==
TTTTYTT
""
Vco
ad
oscillator
2K -Wit
RAM AOdress
RAM
II
+
I
Syncrnous
Detect
~
FSH3
--. .-.
—. . ------
"m
m
M
uemoowano
CLV*
CLV
CLv. 3
Olgital Servo
V,*
J4
~
PW9
Sscrr
1
Sutmde OxIa13
Smsv 4
OCRC
SFSY SO
-
t,
-1
,.a
1,
I
II
Cl C2 Emor Oetecl &
Corr.zclCantrd Flag
i
I
[
1
J
i
I--In *
Smnm
CixR
I
1
I
b
I
~
%
L.P.F
X?al Rcmt
lim!ng
Generator
mm TES WF
*.
JP. RES
7GL
cc+n~:y~:+ns
EMFW ERG
w
42u
Fsx WI
xvm
Rvm
m+io
LCI+3 M-TEL
LVLW
Xvss
XOUT
RVS5 MUTER
LVS2
1
(NC)
-13-
.:. ,....

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