Sharp ER-04RP Service Manual page 8

ER--O4RP
3) Connection with the SRN interface
The control circuit shares the data bus with the SRN interface circuit,
and hardware connection is established between them using ~,
~, and other control signals.
Logic drive power of +5V and SRN bias voltage of +12V are supplied
from the power supply unit.
The SRN interface circuit is not backed up by the VRAM power.
) 1 1
DO-D7
\
w lap
Ra
10P w
-
Wu
DATA
Itvour
~(liuq
-
m(sdq
Printer con-
fflc
-m
(P-11)
*
(l MbPs)
ND(CS)
w
10P -
-ruuurlRIJ
*
lop U&
b
Am
ml
*
Ael
I
6P
I
fi
b w
r
I
+W
(~)
+24V ( 0.M)
+12V ( 150rnA)
Fig.5-3 SRN interfacelprinter controller signal diagram
Interface sianal descrit)tion
1.
2.
3.
4.
5.
6.
7.
S~R
The SRN interface is reset with a low state of signal. The CPU
resets the SRN interface any time through the printer controller
P03 port.
RESET
Reset signal.
This signal is at a high during the power ready state (when
+5V*5% is secured) and low otherwise.
——
RD, WR
Signals for data read/write between the SRN interface and the
controller.
SRNS
SRN interface select signal
DO- D7
Data bus
TRRQ
interrupt request signal from the SRN interface to the controller
Power supply
+5V : Logic drive power +5Vti"/0, 250mA
+12V: SRN line bias circuit power 12V~l Y0,150mA
'RNS ~
i
Aao,l
m
+
max120ns
T
Read data
i
min50rts
Write data
4)
Initial reset and power down interrupt circuit
IC3 is for generating a power down interrupt and a reset signal. When
the supply voltage drops due to a power failure or other cause, the
circuit works to detect the voltage drop and stores necessary data in
the RAM before going into the power down mode.
As shown in the timing chafi, when Vcc drops to 4.6V at the time of a
power failure, the voltage drop is detected, causing the IC to
generate a power down interrupt signal, which is sent to the CPU.
In response to the interrupt signal, the CPU issues the data and other
necessary information in the buffer to the RAM. This process is com-
pleted in about 500msec.
Upon completing the execution of the backup sequence, the CPU
sends out signal RESET OUT through the port (P37), putting itself in
a hardware reset state to prevent it from operating in an unstable
condition.
Also, when the power down prwess is entered, the watchdog timer is
cleared, and WD is issued in 4msec, while in about 900msec a power
down reset is caused, thus providing a ttiple fail-safe mechanism.
[1-4H1
v;
1
,
[1.
().
Fig.5-5 Reset and power down interrupt circuit
Voc(5V)
t~
Abaut4.6V I
I
m
7
Povver down
interrupt
P37
J
RESHOW
+
WD
I
Fig.5-6 Timing chart
MB62H149AC gate &ray timing
Fig.5-4 SRN intedace data write/read timings
-6-