Pci Timing Settings; Integrated Peripherals - VIA Mainboard CX700M Chipset Based Series User Manual

M/b for via c7 processor family
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VGA Share Memory Size
This BIOS feature controls the amount of system memory that is allocated to the integrated
graphics processor when the system boots up. The settings are 32MB,64MB ,128MBand
Disabled.
Select Display Device
This item can provide the single or multi display output. The settings are optional CRT, TV,
DVI, HDTV, HDMI, CRT+DVI, DVI+HDTV, TV+DVI, CRT+HDMI, HDTV+HDMI,
HDMI+TV.
3-6-3

PCI Timing Settings

PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Post Write
PCI Delay Transaction
DRDY-Timing
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7

Integrated Peripherals

OnChip IDE Function
OnChip Device Function
OnChip IO Function
Init Display First
↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
OnChip SIO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or on-chip VGA first. The
settings are: PCI Slot, AGP Slot, On-Chip VGA.
Phoenix – AwardBIOS CMOS Setup Utility
PCI Timing Settings
Disabled
Disabled
Enabled
Enabled
Slowest
F6:Optimized Defaults
Phoenix – AwardBIOS CMOS Setup Utility
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
Menu Level >>
F7:Standard Defaults
Menu Level >
24
Item Help
Item Help

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