Dram Timing Setting; Vga Timing Settings - VIA Mainboard CX700M Chipset Based Series User Manual

Please refer to section 3-6-3
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.

3-6-1 DRAM Timing Setting

System performance
RAS Active Time
RAS Precharge Time
RAS to CAS Delay
DRAM CAS Latency
Bank Interleave
Write Recovery Time
DRAM Command Rate
↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T, 2.5T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in
the system. The settings are: 2T and 3T.

3-6-2 VGA Timing Settings

VGA Share Memory Size
Direct Frame Buffer
Select Display Device
TV_Type
TV_Connector
HDTV_Type
HDTV_Connector
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Setting
By SPD
13T
3T
3T
4.0T
Disabled
5T
2T
Phoenix – AwardBIOS CMOS Setup Utility
AGP Timing Settings
64MB
Disabled
CRT
NTSC
CVBS
HDTV 720P
Pr/Y/Pb
F6:Optimized Defaults
Menu Level >>
Menu Level >>
F7:Standard Defaults
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