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LVDS Flat Panel Signals
Signal
Pin#
Pin Type
LVDS_PPEN
111
O CMOS
LVDS_BLEN
112
O CMOS
LVDS_BLT_CTRL/GP_PWM_OUT0
123
O CMOS
LVDS_A0+
99
eDP0_TX0+
O LVDS
LVDS_A0-
101
eDP0_TX0-
LVDS_A1+
103
eDP0_TX1+
O LVDS
LVDS_A1-
105
eDP0_TX1-
LVDS_A2+
107
eDP0_TX2+
O LVDS
LVDS_A2-
109
eDP0_TX2-
LVDS_A3+
113
eDP0_TX3+
O LVDS
LVDS_A3-
115
eDP0_TX3-
LVDS_A_CLK+
119
eDP0_AUX+
O LVDS
LVDS_A_CLK-
121
eDP0_AUX-
LVDS_B0+
100
eDP1_TX0+
O LVDS
LVDS_B0-
102
eDP1_TX0-
LVDS_B1+
104
eDP1_TX1+
O LVDS
LVDS_B1-
106
eDP1_TX1-
LVDS_B2+
108
eDP1_TX2+
O LVDS
LVDS_B2-
110
eDP1_TX2-
LVDS_B3+
114
eDP1_TX3+
O LVDS
LVDS_B3-
112
eDP1_TX3-
LVDS_B_CLK+
120
eDP1_AUX+
O LVDS
LVDS_B_CLK-
122
eDP1_AUX-
LVDS_DID_CLK/GP_I2C_CLK
127
I/O OD CMOS
LVDS_DID_DAT/GP_I2C_DAT
125
I/O OD CMOS
LVDS_BLC_CLK/eDP1_HPD#
128
I/O OD CMOS
LVDS_BLC_DAT/eDP0_HPD#
126
I/O OD CMOS
DisplayPort Interface Signals
Signal
Pin#
Pin Type
DP_LANE3-
133
O PCIE
DP_LANE3+
131
DP_LANE2-
145
O PCIE
DP_LANE2+
143
DP_LANE1-
139
O PCIE
DP_LANE1+
137
DP_LANE0-
151
O PCIE
DP_LANE0+
149
DP_AUX-
140
I/O PCIE
DP_AUX+
138
DP_HDMI_HPD#
153
I CMOS
HDMI Interface Signals
Signal
Pin#
Pin Type
TMDS_CLK-
133
O TMDS
TMDS_CLK+
131
TMDS_LANE0-
145
O TMDS
TMDS_LANE0+
143
TMDS_LANE1-
139
O TMDS
TMDS_LANE1+
137
TMDS_LANE2-
151
O TMDS
TMDS_LANE2+
149
HDMI_CTRL_CLK
152
I/O OD CMOS
HDMI_CTRL_DAT
150
I/O OD CMOS
DP_HDMI_HPD#
153
I CMOS
Chapter 2 Hardware Installation
Pwr Rail /Tolerance
BT700
Connect to enable control of LVDS panel power circuit
3.3V/3.3V
Connect to enable control of LVDS panel backlight power circuit.
3.3V/3.3V
Connect to brightness control of LVDS panel backlight power circuit.
3.3V/3.3V
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
Connect to LVDS connector
LVDS
3.3V/3.3V
PU 2.2K to 3.3V
Connect to DDC clock of LVDS panel
3.3V/3.3V
PU 2.2K to 3.3V
Connect to DDC clock of LVDS panel
3.3V/3.3V
NC
3.3V/3.3V
NC
Pwr Rail /Tolerance
BT700
Connect AC Coupling Capacitors 0.1uF to Device
DP
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
DP
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
DP
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
DP
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device, PU 100K to 3.3V
DP
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device, PD 100K to GND
3.3V/3.3V
PU 10K to 3.3V
Pwr Rail /Tolerance
BT700
Connect AC Coupling Capacitors 0.1uF to Device
TMDS
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
TMDS
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
TMDS
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
TMDS
AC coupled off Module
Connect AC Coupling Capacitors 0.1uF to Device
3.3V/3.3V
PU 2.2K to 3.3V
3.3V/3.3V
PU 2.2K to 3.3V
3.3V/3.3V
PU 10K to 3.3V
Chapter 2
Carrier Board
Description
Controls panel power enable.
Controls panel Backlight enable.
Primary functionality is to control the panel backlight brightness via pulse width modulation (PWM).
When not in use for this primary purpose it can be used as General Purpose PWM Output.
LVDS primary channel differential pair 0.
Display Port primary channel differential pair 0.
LVDS primary channel differential pair 1.
Display Port primary channel differential pair 1.
LVDS primary channel differential pair 2.
Display Port primary channel differential pair 2.
LVDS primary channel differential pair 3.
Display Port primary channel differential pair 3.
LVDS primary channel differential pair clock lines.
Display Port primary auxiliary channel.
LVDS secondary channel differential pair 0.
Display Port secondary channel differential pair 0.
LVDS secondary channel differential pair 1.
Display Port secondary channel differential pair 1.
LVDS secondary channel differential pair 2.
Display Port secondary channel differential pair 2.
LVDS secondary channel differential pair 3.
Display Port secondary channel differential pair 3.
LVDS secondary channel differential pair clock lines.
Display Port secondary auxiliary channel.
Primary functionality is DisplayID DDC clock line used for LVDS flat panel detection. If primary functionality is not used it can be as General Purpose I²C bus clock line.
Primary functionality DisplayID DDC data line used for LVDS flat panel detection. If primary functionality is not used it can be as General Purpose I²C bus data line.
Control clock signal for external SSC clock chip. If the primary functionality is not used, it can be used as an embedded DisplayPort secondary Hotplug detection.
Control data signal for external SSC clock chip. If the primary functionality is not used, it can be used as an embedded DisplayPort primary Hotplug detection.
Carrier Board
Description
DisplayPort differential pair lines lane 3.
DisplayPort differential pair lines lane 2.
DisplayPort differential pair lines lane 1.
DisplayPort differential pair lines lane 0.
Auxiliary channel used for link management and device control. Differential pair lines.
Hot plug detection signal that serves as an interrupt request.
Carrier Board
Description
TMDS differential pair clock lines.
TMDS differential pair lines lane 0.
TMDS differential pair lines lane 1.
TMDS differential pair lines lane 2.
DDC based control signal (clock) for HDMI device.
Note: Level shifters must be implemented on the carrier board for this signal in order to be compliant with the HDMI Specification.
DDC based control signal (data) for HDMI device.
Note: Level shifters must be implemented on the carrier board for this signal in order to be compliant with the HDMI Specification
Hot plug detection signal that serves as an interrupt request.
15
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