Sony HCD-FL5D Service Manual page 109

Dvd deck receiver
Table of Contents

Advertisement

Pin No.
Pin Name
VSS
48
WMD0
49
PAGE2
50
51
VSS
PAGE1, PAGE0
52, 53
BOOT
54
BTACT
55
BST
56
MOD1
57
MOD0
58
EXLOCK
59
VDDI
60
VSS
61
A17, A16
62, 63
A15 to A13
64 to 66
GP10
67
DECODE
68
AUDIO
69
VDDI
70
71
VSS
D15 to D12
72 to 75
VDDE
76
D11 to D8
77 to 80
81
VSS
A9, A12 to A10
82 to 85
86
TDO
TMS
87
XTRST
88
TCK
89
90
TDI
VSS
91
A8 to A3
92 to 97
D7, D6
98, 99
100
VDDI
VSS
101
102 to 105
D5 to D2
VDDE
106
107, 108
D1, D0
A2, A1
109, 110
VSS
111
A0
112
113
PM
SDI3
114
SDI4
115
I/O
Ground terminal
I
S-RAM wait mode setting terminal Fixed at "L" in this set
O
Page selection signal output terminal Not used
Ground terminal
O
Page selection signal output terminal Not used
I
Boot mode control signal input terminal Not used
O
Boot mode state display signal output terminal Not used
I
Boot trap signal input from the digital audio interface receiver
I
PLL input frequency select terminal
I
Mode setting terminal
I
PLL lock error and data error flag input from the digital audio interface receiver
Power supply terminal (+3.3V)
Ground terminal
O
Address signal output terminal Not used
O
Address signal output to the S-RAM
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter
O
Not used
O
Decode signal output to the system controller
I
Bit 1 input terminal of channel status from the digital audio interface receiver
Power supply terminal (+3.3V)
Ground terminal
I/O
Two-way data bus with the S-RAM
Power supply terminal (+3.3V)
I/O
Two-way data bus with the S-RAM
Ground terminal
O
Address signal output to the S-RAM
O
Simple emulation data output terminal Not used
I
Simple emulation data input start/end detection signal input terminal Not used
I
Simple emulation asychronous break input terminal Not used
I
Simple emulation clock signal input terminal Not used
I
Simple emulation data input terminal Not used
Ground terminal
O
Address signal output to the S-RAM
I/O
Two-way data bus with the S-RAM
Power supply terminal (+3.3V)
Ground terminal
I/O
Two-way data bus with the S-RAM
Power supply terminal (+3.3V)
I/O
Two-way data bus with the S-RAM
O
Address signal output to the S-RAM
Ground terminal
O
Address signal output to the S-RAM
I
PLL reset signal input from the digital audio interface receiver
I
Audio serial data input terminal Not used
I
Audio serial data input terminal Not used
Description
"L": 384fs, "H": 256fs (fixed at "H" in this set)
"L": single chip mode, "H": use prohibition (fixed at "L" in this set)
HCD-FL5D
109

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents