Block Diagram - Casio QT-6100 Service Manual

8-7-2. Block Diagram

CPU
I cache
CPG
INTC
SCI
(SCIF)
RTC
TMU
PCIC
(PCI)DMAC
32-bit
PCI
address/
data
UBC
Lower 32-bit data
Cache and
ITLB UTLB
TLB
controller
BSC
External (SH) bus
interface
32-bit
26-bit
SH bus
SH bus
data
address
— 52 —
FPU
O cache
DMAC
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB: Unified TLB (translation lookaside buffer)
RTC: Realtime clock
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
TMU: Timer unit
UBC: User break controller
PCIC: PCI bus controller