Bd Board Pin Description - Sony CDP-XA30ES Service Manual

• BD BOARD IC351 CXP84124-068Q (SYSTEM CONTROL)
Pin No. Pin Name
1 A3
2 A4
3 A5
4 A6
5 A7
6 A8
7 A9
8 A10
9 A11
10 A12
11 WE
12
NC
13 NC
14 LED-PLAY
15 LED-PAUSE
16 LED-FILTER
17 SPDL-MUTE
18 SHIFT-ON/OFF
19 VOL UP
20 VOL DOWN
21 BLANK
22
FL D0
23
FL D1
24
FL D2
25
FL CLK
26
FL WR
27 SENSER SW
28 SENSER
29
LIMIT OUT
30
RESET
31
XTALI
32 XTALO
33
VSS
34
TX
35 TEX
36
AVSS
37
AVREF
38 ADJ/AFADJ
39
K0
40
K1
41 K2
I/O
O
O
O
O
O
Address signal output to the static RAM (IC352)
O
O
O
O
O
O Write enable signal output to the static RAM (IC352)
O Not used (open)
O Not used (open)
( LED (D871) drive signal output terminal "H": LED on
O
O
P LED (D872) drive signal output terminal "H": LED on
O FILTER LED (D873) drive signal output terminal "H": LED on
O Mute signal output to the spindle motor driver (IC102, 104)
O Reset signal output to the CXD2562Q-CS (IC302) "L": reset
O Volume up control signal output to the volume control motor driver (IC354)
O Volume down control signal output to the volume control motor driver (IC354)
O Blank signal output to the fluorescent indicator tube driver (IC801 to IC803)
O Serial data output to the fluorescent indicator tube driver (IC803)
O Serial data output to the fluorescent indicator tube driver (IC802)
O Serial data output to the fluorescent indicator tube driver (IC801)
O Serial data transfer clock signal output to the fluorescent indicator tube driver (IC801 to IC803)
O Read/write select signal output to the fluorescent indicator tube driver (IC801 to IC803)
O
On/off control signal output to the stabilizer detect sensor (IC361) "H": on
I Detect signal input from the stabilizer detect sensor (IC361) "H": on
Detection input from the sled limit-out detect switch
I
The optical pick-up is outer position when "L" Not used (fixed at "L")
System reset signal input from the reset signal generator (IC206) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
I Main system clock input terminal (4 MHz)
O Main system clock output terminal (4 MHz)
— Ground terminal
O Sub system clock output terminal Not used (open)
I Sub system clock input terminal Not used (fixed at "L")
— Ground terminal (for A/D converter)
I Reference voltage input terminal (+5V)
I Setting terminal for the test mode "L" active
I Key input terminal (A/D input) (fixed at "H")
Key input terminal (A/D input)
I
P MODE, TIME keys (S819S820) input
Key input terminal (A/D input)
I
ERASE, CHECK, CLEAR, FILTER, 0, ) , keys (S801 to S806) input
Function
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