LG 55LM8600 Service Manual page 24

IC100
LG1152D-B1
D18
M0_DDR_A0 M0_DDR_A0
E17
M0_DDR_A1 M0_DDR_A1
E18
M0_DDR_A2 M0_DDR_A2
E20
M0_DDR_A3 M0_DDR_A3
E16
M0_DDR_A4 M0_DDR_A4
D20
M0_DDR_A5
M0_DDR_A5
F16 VCC1.5V_MAIN
M0_DDR_A6 M0_DDR_A6
F19
M0_DDR_A7 M0_DDR_A7
E15
M0_DDR_A8 M0_DDR_A8 R709
D19
M0_DDR_A9 M0_DDR_A9
10K
D14
M0_DDR_A10 M0_DDR_A10
E14
M0_DDR_A11 M0_DDR_RESET_N
M0_DDR_A11
D17
M0_DDR_A12
M0_DDR_A12
F18
M0_DDR_A13 M0_DDR_A13
D16
M0_DDR_A14
M0_DDR_A14
F20
M0_DDR_BA0 M0_DDR_BA0 M0_DDR_CLK
D15
M0_DDR_BA1 M0_DDR_BA1
R705
F17
M0_DDR_BA2
M0_DDR_BA2
200
A17
R700 0
M0_DDR_CLK M0_DDR_CLK
A18 M0_DDR_CLKN
R701 0
M0_DDR_CLKN M0_DDR_CLKN
F15
M0_DDR_CKE M0_DDR_CKE
F21
M0_DDR_ODT
M0_DDR_ODT
D22
M0_DDR_RASN
M0_DDR_RASN
E21
M0_DDR_CLK
M0_DDR_CASN M0_DDR_CASN
D21
M0_DDR_WEN M0_DDR_WEN
R706
E19 200
M0_DDR_RESET_N M0_DDR_RESET_N
M0_DDR_CLKN
B20
M0_DDR_DQSL_P
M0_DDR_DQSL_P
A20
M0_DDR_DQSL_N M0_DDR_DQSL_N
B16
M0_DDR_DQSU_P M0_DDR_DQSU_P
C16
M0_DDR_DQSU_N M0_DDR_DQSU_N
C19
M0_DDR_DML
M0_DDR_DML
C15 M0_DDR_CKE
M0_DDR_DMU
M0_DDR_DMU
C20 R742
M0_DDR_DQ0 M0_DDR_DQ0
B19 10K
M0_DDR_DQ1 M0_DDR_DQ1
C21
M0_DDR_DQ2 M0_DDR_DQ2
B18
M0_DDR_DQ3 M0_DDR_DQ3
A21
M0_DDR_DQ4
M0_DDR_DQ4
C18
M0_DDR_DQ5
M0_DDR_DQ5
B21
M0_DDR_DQ6
M0_DDR_DQ6
A19
M0_DDR_DQ7 M0_DDR_DQ7
B17
M0_DDR_DQ8 M0_DDR_DQ8
C14
M0_DDR_DQ9 M0_DDR_DQ9
A16
M0_DDR_DQ10
M0_DDR_DQ10
B14
M0_DDR_DQ11
M0_DDR_DQ11
B15
M0_DDR_DQ12
M0_DDR_DQ12
A14
M0_DDR_DQ13 M0_DDR_DQ13
C17
M0_DDR_DQ14 M0_DDR_DQ14
A15
M0_DDR_DQ15 M0_DDR_DQ15
E22 SIGN50005 240 R704
M0_DDR_ZQCAL
1%
IC100
LG1152D-B1
C9
M1_DDR_A0
M1_DDR_A0
E9
M1_DDR_A1
M1_DDR_A1
F10
M1_DDR_A2 M1_DDR_A2
F12
M1_DDR_A3 M1_DDR_A3
F8
M1_DDR_A4 M1_DDR_A4 VCC1.5V_MAIN
D11
M1_DDR_A5 M1_DDR_A5
E8
M1_DDR_A6 M1_DDR_A6
E11
M1_DDR_A7 R710
M1_DDR_A7
E7
10K
M1_DDR_A8 M1_DDR_A8
D10
M1_DDR_A9 M1_DDR_A9
C4 M1_DDR_RESET_N
M1_DDR_A10 M1_DDR_A10
C5
M1_DDR_A11 M1_DDR_A11
D8
M1_DDR_A12 M1_DDR_A12
E10
M1_DDR_A13
M1_DDR_A13
C7
M1_DDR_A14
M1_DDR_A14
M1_DDR_CLK
E12
M1_DDR_BA0 M1_DDR_BA0 R707
F7
M1_DDR_BA1 M1_DDR_BA1 200
D9
M1_DDR_BA2 M1_DDR_BA2
M1_DDR_CLKN
A9
R702 0 M1_DDR_CLK
M1_DDR_CLK
B9
R703 0
M1_DDR_CLKN M1_DDR_CLKN
D7
M1_DDR_CKE M1_DDR_CKE
D13
M1_DDR_ODT M1_DDR_ODT
C13 M1_DDR_CLK
M1_DDR_RASN M1_DDR_RASN
E13
M1_DDR_CASN R708
M1_DDR_CASN
D12
M1_DDR_WEN
M1_DDR_WEN 200
F11
M1_DDR_RESET_N M1_DDR_RESET_N M1_DDR_CLKN
C12
M1_DDR_DQSL_P M1_DDR_DQSL_P
C11
M1_DDR_DQSL_N M1_DDR_DQSL_N
A7
M1_DDR_DQSU_P M1_DDR_DQSU_P
B7
M1_DDR_CKE
M1_DDR_DQSU_N M1_DDR_DQSU_N
A11
M1_DDR_DML M1_DDR_DML
C6
M1_DDR_DMU M1_DDR_DMU R741
10K
A12
M1_DDR_DQ0
M1_DDR_DQ0
B11
M1_DDR_DQ1 M1_DDR_DQ1
A13
M1_DDR_DQ2 M1_DDR_DQ2
C10
M1_DDR_DQ3 M1_DDR_DQ3
B12
M1_DDR_DQ4 M1_DDR_DQ4
A10
M1_DDR_DQ5 M1_DDR_DQ5
B13
M1_DDR_DQ6
M1_DDR_DQ6
B10
M1_DDR_DQ7 M1_DDR_DQ7
A8
M1_DDR_DQ8 M1_DDR_DQ8
B4
M1_DDR_DQ9 M1_DDR_DQ9
C8
M1_DDR_DQ10 M1_DDR_DQ10
B5
M1_DDR_DQ11 M1_DDR_DQ11
B6
M1_DDR_DQ12
M1_DDR_DQ12
A5
M1_DDR_DQ13
M1_DDR_DQ13
B8
M1_DDR_DQ14 M1_DDR_DQ14
A6
M1_DDR_DQ15 M1_DDR_DQ15
IC100
LG1152D-B1
D1
M2_DDR_A0
K4
M2_DDR_A1
D2
M2_DDR_A2
E5
M2_DDR_A3
H6
M2_DDR_A4
E4
M2_DDR_A5
J4
M2_DDR_A6
D6
M2_DDR_A7
J5
M2_DDR_A8
D3
M2_DDR_A9
H4
M2_DDR_A10
J6
M2_DDR_A11
K5
M2_DDR_A12
D4
M2_DDR_A13
E6
M2_DDR_BA0
H5
M2_DDR_BA1
F4
M2_DDR_BA2
M2
M2_DDR_CLK
M3
M2_DDR_CLKN
G6
M2_DDR_CKE
F6
M2_DDR_ODT
G5
M2_DDR_RASN
G4
M2_DDR_CASN
F5
M2_DDR_WEN
D5
M2_DDR_RESET_N
H3
M2_DDR_DQSU_P
J1
M2_DDR_DQSU_N
H1
M2_DDR_DQSL_P
H2
M2_DDR_DQSL_N
K3
M2_DDR_DML
F2
M2_DDR_DMU
F1
M2_DDR_DQ0
L1
M2_DDR_DQ1
E3
M2_DDR_DQ2
L2
M2_DDR_DQ3
E1
M2_DDR_DQ4
M1
M2_DDR_DQ5
E2
M2_DDR_DQ6
L3
M2_DDR_DQ7
J3
M2_DDR_DQ8
G1
M2_DDR_DQ9
K2
M2_DDR_DQ10
F3
M2_DDR_DQ11
J2
M2_DDR_DQ12
G2
M2_DDR_DQ13
K1
M2_DDR_DQ14
G3
M2_DDR_DQ15
K6
M2_DDR_ZQCAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
IC700
H5TQ2G83BFR-PBC M0_DDR_VREFCA
VCC1.5V_MAIN
M0_DDR_VREFDQ
DDR3
K4 J9
2Gbit
M0_DDR_A0 A0 VREFCA
L8
M0_DDR_A1 A1
L4
M0_DDR_A2 A2
K3 E2
M0_DDR_A3 A3
VREFDQ
L9
M0_DDR_A4
A4
L3
M0_DDR_A5 A5 R720 VCC1.5V_MAIN
M9 H9
M0_DDR_A6 A6 ZQ
M3
240
M0_DDR_A7 A7
N9 1%
M0_DDR_A8 A8
M4 A3
M0_DDR_A9 A9 VDD_1
H8 A10
M0_DDR_A10
A10/AP VDD_2
M8 D8 C706 0.1uF
M0_DDR_A11
A11 VDD_3
K8 G3 C707 0.1uF
M0_DDR_A12 A12/BC VDD_4
N4 G9 0.1uF
C708
M0_DDR_A13 A13 VDD_5
N8 K2 0.1uF
C709
M0_DDR_A14 A14 VDD_6
K10 C710 0.1uF
VDD_7
M2 C711 0.1uF
VDD_8
J3 M10 C712 0.1uF
M0_DDR_BA0
BA0 VDD_9
K9 VCC1.5V_MAIN
M0_DDR_BA1 BA1
J4
M0_DDR_BA2 BA2
B10
VDDQ_1
F8 C2
M0_DDR_CLK CK VDDQ_2
G8 E3
M0_DDR_CLKN CK VDDQ_3
G10 E10
M0_DDR_CKE
CKE VDDQ_4
H3
CS
G2
M0_DDR_ODT ODT
F4
M0_DDR_RASN RAS
G4
M0_DDR_CASN CAS
H4
M0_DDR_WEN WE
A1
NC_S1
N3 A11
M0_DDR_RESET_N RESET NC_S2
N1
NC_S3
N11
NC_S4
C4
M0_DDR_DQSL_P DQS
D4
M0_DDR_DQSL_N DQS
B8 A2
M0_DDR_DML
DM/TDQS VSS_1
A8 A9
NF/TDQS VSS_2
B2
VSS_3
D9
VSS_4
F3
VSS_5
F9
VSS_6
B4 J2
M0_DDR_DQ0
DQ0 VSS_7
C8 J10
M0_DDR_DQ1 DQ1 VSS_8
C3 L2
M0_DDR_DQ6 DQ2 VSS_9
C9 L10
M0_DDR_DQ7 DQ3 VSS_10
E4 N2
M0_DDR_DQ4 DQ4 VSS_11
E9 N10
M0_DDR_DQ3 DQ5 VSS_12
D3
M0_DDR_DQ2
DQ6
E8
M0_DDR_DQ5
DQ7
B3
VSSQ_1
A4 B9
NC_1 VSSQ_2
F2 C10
NC_2 VSSQ_3
F10 D2
NC_3 VSSQ_4
H2 D10
NC_4 VSSQ_5
H10
NC_5
J8
NC_6
IC701
M1_DDR_VREFCA
H5TQ2G83BFR-PBC
VCC1.5V_MAIN
M1_DDR_VREFDQ
DDR3
K4 2Gbit J9
M1_DDR_A0 A0 VREFCA
L8
M1_DDR_A1
A1
L4
M1_DDR_A2 A2
K3 E2
M1_DDR_A3 A3 VREFDQ
L9
M1_DDR_A4 A4
L3
M1_DDR_A5 A5 R721 VCC1.5V_MAIN
M9 H9
M1_DDR_A6 A6 ZQ
M3 240
M1_DDR_A7
A7 1%
N9
M1_DDR_A8
A8
M4 A3
M1_DDR_A9 A9 VDD_1
H8 A10
M1_DDR_A10 A10/AP VDD_2
M8 D8 0.1uF
C713
M1_DDR_A11 A11 VDD_3
K8 G3 0.1uF
C714
M1_DDR_A12 A12/BC VDD_4
N4 G9 C715 0.1uF
M1_DDR_A13 A13 VDD_5
N8 K2 C716 0.1uF
M1_DDR_A14
A14 VDD_6
K10 C717 0.1uF
VDD_7
M2 C718 0.1uF
VDD_8
J3 M10 0.1uF
C719
M1_DDR_BA0 BA0 VDD_9
K9
VCC1.5V_MAIN
M1_DDR_BA1 BA1
J4
M1_DDR_BA2 BA2
B10
VDDQ_1
F8 C2
M1_DDR_CLK
CK VDDQ_2
G8 E3
M1_DDR_CLKN CK VDDQ_3
G10 E10
M1_DDR_CKE CKE VDDQ_4
H3
CS
G2
M1_DDR_ODT ODT
F4
M1_DDR_RASN
RAS
G4
M1_DDR_CASN CAS
H4
M1_DDR_WEN WE
A1
NC_S1
N3 A11
M1_DDR_RESET_N RESET NC_S2
N1
NC_S3
N11
NC_S4
C4
M1_DDR_DQSL_P
DQS
D4
M1_DDR_DQSL_N DQS
B8 A2
M1_DDR_DML DM/TDQS VSS_1
A8 A9
NF/TDQS VSS_2
B2
VSS_3
D9
VSS_4
F3
VSS_5
F9
VSS_6
B4 J2
M1_DDR_DQ0 DQ0 VSS_7
C8 J10
M1_DDR_DQ1 DQ1 VSS_8
C3 L2
M1_DDR_DQ6 DQ2 VSS_9
C9 L10
M1_DDR_DQ7 DQ3 VSS_10
E4 N2
M1_DDR_DQ4
DQ4 VSS_11
E9 N10
M1_DDR_DQ3 DQ5 VSS_12
D3
M1_DDR_DQ2 DQ6
E8
M1_DDR_DQ5 DQ7
B3
VSSQ_1
A4 B9
NC_1 VSSQ_2
F2 C10
NC_2 VSSQ_3
F10 D2
NC_3 VSSQ_4
H2 D10
NC_4 VSSQ_5
H10
NC_5
J8
NC_6
M2_DDR_A0
M2_DDR_A1
M2_DDR_A2
M2_DDR_A3
M2_DDR_A4
M2_DDR_A0
M2_DDR_A5
M2_DDR_A1
M2_DDR_A6
M2_DDR_A2
M2_DDR_A3 M2_DDR_A7
M2_DDR_A4 M2_DDR_A8
M2_DDR_A9
M2_DDR_A5
M2_DDR_A10
M2_DDR_A6
M2_DDR_A11
M2_DDR_A7
M2_DDR_A12
M2_DDR_A8
M2_DDR_A9 M2_DDR_A13
M2_DDR_A10 VCC1.5V_DE M2_DDR_CKE
M2_DDR_A11
M2_DDR_A12
R743
M2_DDR_BA0
M2_DDR_A13
R714 10K
M2_DDR_BA1
10K M2_DDR_BA2
M2_DDR_BA0
M2_DDR_RESET_N M2_CLK
M2_DDR_BA1
M2_CLKN
M2_DDR_BA2
M2_DDR_CKE
M2_DDR_CLK M2_CLK
M2_DDR_CLKN
R715
M2_DDR_CKE M2_DDR_ODT
150
M2_DDR_RASN
M2_DDR_CASN
M2_DDR_ODT
M2_CLKN
M2_DDR_WEN
M2_DDR_RASN
M2_DDR_CASN
M2_DDR_RESET_N
M2_DDR_WEN
M2_DDR_RESET_N
M2_DDR_DQSL_P
R716 0 M2_DDR_DQSL_N
M2_DDR_DQSU_P M2_DDR_CLK M2_CLK
R717 0
M2_DDR_DQSU_N M2_DDR_CLKN M2_CLKN
M2_DDR_DQSU_P
M2_DDR_DQSU_N
M2_DDR_DQSL_P
M2_DDR_DQSL_N
M2_DDR_DML
M2_DDR_DMU
M2_DDR_DML
M2_DDR_DMU
M2_DDR_DQ0
M2_DDR_DQ1
M2_DDR_DQ0
M2_DDR_DQ2
M2_DDR_DQ1
M2_DDR_DQ2 M2_DDR_DQ3
VCC1.5V_DE VCC1.5V_DE
M2_DDR_DQ3 M2_DDR_DQ4
M2_DDR_DQ4 M2_DDR_DQ5
M2_DDR_VREFCA M2_DDR_VREFDQ
M2_DDR_DQ6
M2_DDR_DQ5
M2_DDR_DQ7
M2_DDR_DQ6
M2_DDR_DQ7
M2_DDR_DQ8 M2_DDR_DQ8
M2_DDR_DQ9 M2_DDR_DQ9
M2_DDR_DQ10 M2_DDR_DQ10
M2_DDR_DQ11
M2_DDR_DQ11
M2_DDR_DQ12
M2_DDR_DQ12
M2_DDR_DQ13
M2_DDR_DQ13
M2_DDR_DQ14
M2_DDR_DQ14
M2_DDR_DQ15 M2_DDR_DQ15
240 R711
1%
IC703
H5TQ2G83BFR-PBC
VCC1.5V_MAIN
DDR3
M0_1_DDR_VREFCA K4
M0_DDR_VREFCA
M0_DDR_A0 A0 2Gbit VREFCA
L8
M0_DDR_A1 A1
L4
M0_DDR_A2 A2
K3
M0_DDR_A3 A3
VREFDQ
L9
M0_DDR_A4
A4
L3
M0_DDR_A5 A5
M9
M0_DDR_A6 A6
M3
M0_DDR_A7 A7
N9
M0_DDR_A8 A8
M4
M0_DDR_A9 A9 VDD_1
H8
M0_DDR_A10
A10/AP VDD_2
M8
M0_DDR_A11
A11 VDD_3
K8
M0_DDR_A12 A12/BC VDD_4
N4
M0_DDR_A13 A13 VDD_5
N8
M0_DDR_A14 A14 VDD_6
VDD_7
VDD_8
J3
M0_DDR_BA0
BA0 VDD_9
K9
VCC1.5V_MAIN
M0_DDR_BA1 BA1
J4
M0_DDR_BA2 BA2
M0_1_DDR_VREFDQ
M0_DDR_VREFDQ
VDDQ_1
F8
M0_DDR_CLK CK VDDQ_2
G8
M0_DDR_CLKN CK VDDQ_3
G10
M0_DDR_CKE
CKE VDDQ_4
H3
CS
G2
M0_DDR_ODT ODT
F4
M0_DDR_RASN RAS
G4
M0_DDR_CASN CAS
H4
M0_DDR_WEN WE
NC_S1
N3
M0_DDR_RESET_N RESET NC_S2
NC_S3
NC_S4
C4
M0_DDR_DQSU_P DQS
D4
M0_DDR_DQSU_N DQS
B8
M0_DDR_DMU
DM/TDQS VSS_1
A8
NF/TDQS VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
B4
M0_DDR_DQ10
DQ0 VSS_7
C8
M0_DDR_DQ13 DQ1 VSS_8
C3
M0_DDR_DQ14 DQ2 VSS_9
C9
M0_DDR_DQ11 DQ3 VSS_10
E4
M0_DDR_DQ15 DQ4 VSS_11
E9
M0_DDR_DQ9 DQ5 VSS_12
D3
M0_DDR_DQ8
DQ6
E8
M0_DDR_DQ12
DQ7
VSSQ_1
A4
NC_1 VSSQ_2
F2
NC_2 VSSQ_3
F10
NC_3 VSSQ_4
H2
NC_4 VSSQ_5
H10
NC_5
J8
NC_6
IC704
H5TQ2G83BFR-PBC
VCC1.5V_MAIN
DDR3
M1_1_DDR_VREFCA K4
M1_DDR_VREFCA M1_DDR_A0 A0 VREFCA
2Gbit
L8
M1_DDR_A1
A1
L4
M1_DDR_A2 A2
K3
M1_DDR_A3 A3 VREFDQ
L9
M1_DDR_A4 A4
L3
M1_DDR_A5 A5
M9
M1_DDR_A6 A6
M3
M1_DDR_A7
A7
N9
M1_DDR_A8
A8
M4
M1_DDR_A9 A9 VDD_1
H8
M1_DDR_A10 A10/AP VDD_2
M8
M1_DDR_A11 A11 VDD_3
K8
M1_DDR_A12 A12/BC VDD_4
N4
M1_DDR_A13 A13 VDD_5
N8
M1_DDR_A14
A14 VDD_6
VDD_7
VDD_8
J3
M1_DDR_BA0 BA0 VDD_9
K9
VCC1.5V_MAIN
M1_DDR_BA1 BA1
J4
M1_DDR_BA2 BA2
M1_1_DDR_VREFDQ
M1_DDR_VREFDQ
VDDQ_1
F8
M1_DDR_CLK
CK VDDQ_2
G8
M1_DDR_CLKN CK VDDQ_3
G10
M1_DDR_CKE CKE VDDQ_4
H3
CS
G2
M1_DDR_ODT ODT
F4
M1_DDR_RASN
RAS
G4
M1_DDR_CASN CAS
H4
M1_DDR_WEN WE
NC_S1
N3
M1_DDR_RESET_N RESET NC_S2
NC_S3
NC_S4
C4
M1_DDR_DQSU_P
DQS
D4
M1_DDR_DQSU_N DQS
B8
M1_DDR_DMU DM/TDQS VSS_1
A8
NF/TDQS VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
B4
M1_DDR_DQ10 DQ0 VSS_7
C8
M1_DDR_DQ13 DQ1 VSS_8
C3
M1_DDR_DQ14 DQ2 VSS_9
C9
M1_DDR_DQ11 DQ3 VSS_10
E4
M1_DDR_DQ15
DQ4 VSS_11
E9
M1_DDR_DQ9 DQ5 VSS_12
D3
M1_DDR_DQ8 DQ6
E8
M1_DDR_DQ12 DQ7
VSSQ_1
A4
NC_1 VSSQ_2
F2
NC_2 VSSQ_3
F10
NC_3 VSSQ_4
H2
NC_4 VSSQ_5
H10
NC_5
J8
NC_6
IC702
H5TQ1G63DFR-PBC
M2_DDR_VREFCA
N3 M8 M2_DDR_VREFDQ
A0 VREFCA
P7
A1
P3
A2
N2 H1
A3 VREFDQ
P8
A4
P2
A5
R8 L8 R738
SIGN50000 240
A6 ZQ
R2 VCC1.5V_DE
A7
T8
A8
R3 B2
A9 VDD_1
L7 D9 C722
A10/AP VDD_2 0.1uF
R7 G7 C704
A11 VDD_3 0.1uF
N7 K2
C705 0.1uF
A12/BC VDD_4
T3 K8
C720 0.1uF
A13 VDD_5
N1
C721 0.1uF
VDD_6
M7 N9
A15 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
C736 0.1uF
CK VDDQ_2
K7 C1
C737 0.1uF
CK VDDQ_3
K9 C9 C738 0.1uF
CKE VDDQ_4
D2 C739 0.1uF
VDDQ_5
L2 E9 C740 0.1uF
CS VDDQ_6
K1 F1
C741 0.1uF
ODT VDDQ_7
J3 H2
C742 0.1uF
RAS VDDQ_8
K3 H9
C743 0.1uF
CAS VDDQ_9
L3 C744
10uF 10V
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
DQSL NC_6
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
M0_1_DDR_VREFCA
M0_1_DDR_VREFDQ
J9
E2
R739 VCC1.5V_MAIN
H9
ZQ
240
1%
A3
A10 C758 0.1uF
D8
G3
0.1uF
G9 C746
K2
C723 0.1uF
K10
M2 C760 0.1uF
M10
0.1uF
C751
B10
0.1uF
C761
C2
E3
E10 C756 0.1uF
A1
A11
N1
N11
A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10
B3
B9
C10
D2
D10
M1_1_DDR_VREFCA
M1_1_DDR_VREFDQ
J9
E2
R740 VCC1.5V_MAIN
H9
ZQ
240
1%
A3
A10 0.1uF
C757
D8
0.1uF
G3 C752
G9 0.1uF
C753
K2
C754 0.1uF
K10
M2
M10 0.1uF
C755
B10 C745 0.1uF
C2
E3
E10 0.1uF
C759
A1
A11
N1
N11
A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10
B3
B9
C10
D2
D10
LG1152 B0
MAIN DDR 4 50
LGE Internal Use Only