AXIOMTEK EP820 Series User Manual page 53

EP820 All-In-One EPIC Board User's Manual
DRAM RAS# Precharge
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to
retain data.
DRAM Data Integrity Mode
Use this item to set data integrity mode of the DRAM installed in
the system. The default setting is "Non-ECC".
MGM Core Frequency
Use this item to set the clock ratio of CPU and system.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However,
if any program writes to this memory area, a system error may
result. The default value is "Disabled".
Video BIOS Cacheable
This item allows you to change the Video BIOS location from ROM
to RAM. Video Shadow will increase the video speed.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user
information of peripherals that need to use this area of system
memory usually discusses their memory requirements.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select "Enabled" to support PCI
specification version 2.1. The options available are "Enabled" and
"Disabled".
AGP Aperture Size (MB)
Use this item to set aperture size of the graphics. The aperture is a
portion of the PCI memory address range dedicated for graphics
memory address space. Host cycles that hit the aperture range are
forwarded to the AGP without any translation. The options
available are "4M"," 8M", "16M", "32M", "64M", "128M" and "256M".
Init Display First
This item allows you to decide whether PCI Slot or AGP to be the
Award BIOS Utility
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