Sony PRS-505 Service Manual page 34

PRS-505
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3 7 63 1515 0
• IC Pin Function Description
MAIN BOARD IC201 R5C807 (MEMORY STICK DUO/SD MEMORY CARD CONTROLLER)
Pin No. Pin Name
1 VCCEN
2 GPIO
3 LED
4 HWSPND
5 RWMODE
6 WAMODE
7 LTLEN
8 TEST
9 CKIN
10 GND
11 RST
12 VCC_ROUT
13 VCC_RIN
14 REGEN
15 INT
16 WAIT/DTACK
17 WR
18 RD
19, 20 EB0, EB1
21 VCC_HOST
22 CS
23 to 30 D15 to D8
TE
L 13942296513
31 to 33 D7 to D5
34 GND
35 to 39 D0 to D4
40 BS
41 A22
42 VCC_ROUT
43 to 47 A21 to A17
48 VCC_HOST
49 A16
50 to 64 A15 to A1
65 A0
66 GND
67 SDCD
68 SDDAT3
69 MDIO11
70 MSDAT0
71 MDIO12
72 MSDAT1
73 VCC_3V
74 MDIO13
75 MSDAT2
76 MDIO14
77 MSDAT3
MDIO15, MDIO19 to
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78 to 84
MDIO24
85 SDWP
86 VCC_ROUT
.
87 MSCLK
88 MDIO17
89 SDCLK
34
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I/O
O +3.3V power supply control signal output terminal
I/O Not used
O Not used
Hardware suspend mode select signal input from the main CPU
I
"L": hardware suspend mode
Read-write timing mode select signal input terminal
I
"H": maximum cycle time
WAIT/DTACK mode select signal input terminal
I
"L": DTACK mode, "H": WAIT mode
Little/big endian select signal input terminal
I
"L": little endian mode, "H": big endian mode
I Test mode terminal
I Host colck signal input from the main CPU
- Ground terminal
I Reset signal input terminal
- Power supply terminal (+1.8V)
- Power supply terminal (+1.8V)
I Internal regulator control signal input terminal
O Interrupt request signal output to the main CPU
O Data acknowledge signal output terminal
I Write enable signal input from the main CPU
I Read enable signal input from the main CPU
I Byte enable signal input terminal
- Power supply terminal (+3.3V)
I Chip select signal input from the address decoder
I/O Two-way data bus with the USB controller, main CPU, SD-RAM and NOR fl ash memory
Two-way data bus with the USB controller, main CPU, NAND fl ash memory, SD-RAM and
I/O
NOR fl ash memory
- Ground terminal
Two-way data bus with the USB controller, main CPU, NAND fl ash memory, SD-RAM and
I/O
NOR fl ash memory
I Bus cycle start signal input terminal
I Address signal input terminal
- Power supply terminal (+1.8V)
I Address signal input terminal
- Power supply terminal (+3.3V)
I Address signal input terminal
I Address signal input from the main CPU
I Address signal input terminal
- Ground terminal
SD memory card detect signal input from the SD memory card slot
I
"L": SD memory card slot in
I/O Two-way 4-bits data bus with the SD memory card slot
I/O Not used
I/O Two-way data bus with the memory stick duo slot
I/O Not used
I/O Two-way data bus with the memory stick duo slot
- Power supply terminal (+3.3V)
I/O Not used
I/O Two-way data bus with the memory stick duo slot
I/O Not used
I/O Two-way data bus with the memory stick duo slot
I/O Not used
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I SD memory card write protect switch signal input from the SD memory card slot
y
- Power supply terminal (+1.8V)
i
O Serial clock signal output to the memory stick duo slot
I/O Not used
O Serial clock signal output to the SD memory card slot
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2 9
8
Description
Not used
Fixed at "H" in this set
Fixed at "L" in this set
Fixed at "L" in this set
Normally fi xed at "L"
"L": reset
"L": regulator on
Not used
Not used
Q Q
3 6 7 1 3 1 5
Not used
Not used
Not used
Not used
Not used
co
.
9 4 2 8
Fixed at "H" in this set
0 5 8 2 9 9 4 2 8
m
9 9
9 9