LG LAC6700R Service Manual page 21

Pin Name in Micom
51 AVSS
52 P157/ANI15
53 P156/ANI14
54 P155/ANI13
55 P154/ANI12
56 P153/ANI11
57 P152/ANI10
58 P151/ANI9
59 P150/ANI8
60 P27/ANI7
61 P26/ANI6
62 P25/ANI5
63 P24/ANI4
64 P23/ANI3
65 P22/ANI2
66 P21/ANI1
67 P20/ANI0
68 P130
69 P131/TI06/TO06
70 P04/SCK10'/SCL1
71 P03/SI10/RxD1/SDA1
72 P02/SO10/TXD1
73 P01/TO00
74 P00/TI00
75 P145/TI07/TO07
76 P144/SO20/TxD2
77 P143/SI20/RxD2/SDA2
78 P142/SCK20'/SCL2
79 P141/PCLBUZ1/INTP7
80 P140/PCLBUZ0/INTP6
81 P120/INTP0/EXLVI
82 P47/INTP2 PFLMD0_
83 P46/INTP1/TI05/TO05
84 P45/SO01
85 P44/SI01
86 P43/SCK01'
87 P42/TI04/TO04
88 P41/TOOL1
89 P40/TOOL0
90 RESET'
91 P124/XT2
92 P123/XT1
93 FLMD0
94 P122/X2/EXCLK
95 P121/X1
96 REGC
97 VSS
98 EVSS0
99 VDD
100 EVDD0
LGE Internal Use Only
Name in Model Enable I/O I/O setted Output Format
PKEY1 I/O
PKEY2 I/O
PLEVEL_METER I/O
PSMETER I/O
PQUALTY I/O
PEJECT I/O
PDIM_OUT I/O
PLIGHT I/O
PAUX_MUTE I/O
PAUDIO_MUTE I/O
PTEL_MUTE I/O
PREMOTE I/O
PPWR I/O
PRDS_DI I/O
PDIM_IN I/O
PEEPROM_CE I/O
PPLL_CE O
PSD_ST I/O
PART_EN I/O
PART_RX I/O
PART_TX I/O
PFRT_DETECT I/O
PFRT_OPEN I/O I
PFRT_RST I/O
PCDP_DO I/O
PCDP_DI I/O
PCDP_CLK I/O
PFRT_CE I/O
PBEEP I/O
PEXLVI I/O
CTR I/O
PRDS_CLK I/O
PFRT_DO I/O
PFRT_DI I/O
PFRT_CLK I/O
PANT I/O
Download_CLK I/O
Download_IO I/O
- -
- I
- I
-
- I
- I
- -
-
-
-
-
I - Key #1 line input
I - Key #2 line input
I - Level meter input
I - Radio station's strength signal input
I - Connect to tuner pack QUALITY
I - Eject key input
O CMOS Dimmer output
O CMOS Backlight control output
O CMOS AUX mute
O CMOS VR IC <--> PWR AMP mute
O CMOS Telephone mute input
O CMOS External amp on
O CMOS Power on
I - From tuner pack, RDS data input
I - Dimmer input
O CMOS EEPROM Chip select
O CMOS PLL chip select
I - SD level input from Tuner pack
O - ART Enable input
I - Data input for ART
I CMOS Data output for ART
I - Front detaching/attaching detect
- Front open/close detect
O CMOS Front micom(LCD drv) reset
O CMOS Data output for CDP
I - Data input for CDP
O CMOS CLK output for CDP
I - Data enable output to front micom(LCD drv)
O CMOS Buzzer output
I - Low voltage detector(Connect to Vdd)
Disc download FLMD0 control(Connect to
O CMOS
FLMD0(Pin93))
I - From tuner pack, RDS data input
O CMOS Data output to front micom(LCD drv)
I - Data input from front micom(LCD drv)
O CMOS CLK output to front micom(LCD drv)
O CMOS Antena control output
- - CLK for onboard debugger
Data I/O for flash memory programmer
- -
(Pull-up register(10K))
- - System reset input
I - Sub clock 32.768 KHz
I - Sub clock 32.768 KHz
Flash memory programming mode setting
I - X-tal 19.2 MHz
I - X-tal 19.2 MHz
Connect to VSS via a capacitor (0.47 to 1µF)
Ground
Ground Potential for Ports
Positive power supply (+5V)
Positive power supply (+5V) For Ports
Copyright © 2007 LG Electronics. Inc. All right reserved.
2-16
Description
Only for training and service purposes