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IC BLOCK DIAGRAM & DESCRIPTION
IC822 LC3816161ET-70-MPB (Synchronous DRAM)
CLK
35
20~24
ADD
27~32
LCKE
LRAS
35
CLK
No.
35
CLK
18
CS
34
CKE
20,21~24
A0 to A10/AP
27~32
19
BA
17
RAS
16
CAS
15
WE
14,36
L(U)DQM
2,3,5,6,8,9,11,
DQ0 to 15
12,39,40,42,43,
45,46,48,49
1,50
VDD/VSS
7,41
VDDQ/VSSQ
37
N.C/RFU
Bank select
LCBR
LWE
LCAS
Timing register
34
18
17
CKE
CS
RAS
Pin
Name
System clock
Chip select
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data mask ensble
Data input/output
Power supply/ground
Output buffer power/ground
No connection
Data input register
512K
X
16
512K
16
X
Column decoder
Latency & burst length
Progremming register
LWCBR
16
15
14,36
CAS
WE
L(U)DQM
Active on the positive going edge to sample all inputs.
Disables or enable device operation by masking or enablin
all inputs except CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock
cycle. CKE should be enable at least one cycle prior to no
command. Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pin.
Row address : RA0 to RA10, column address : CA0 to CA7
Select bank to be activated during row address latchtime.
Select bank for read/write during column address latch time.
Latches row address on the positive going edge of the CLK
with RAS low. Enable row access & precharge.
Latches column address on the positive going edge of the
CLK with CAS low. Enable column access.
Enable write operation and row precharge.
Latches data in strting from CAS, WE active.
Makes data output Hi-Z, t SHZ after the clock and masks
the output. Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for theinput buffer and the core logic.
Isolated power supply and ground for the output buffers
to proxide improved noise immunity.
This pin is recommended to be left no connection on the
device.
- 32 -
14 LDQM
2,3,
5,6,
8,9,
11,12,
39,40,
42,43,
45,46,
48,49
LDQM
Input Function
LWE
DQi
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