Sanyo VPC-CG6EX Service Manual page 4

3. IC901 (V Driver)
A V driver (IC901) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
In addition the XV1-XV13 signals which are output from IC101
are vertical transfer clocks, and the XSG signal is superim-
posed onto XV1, XV3 and XV5 at IC901 in order to generate
a ternary pulse. In addition, the XSUB signal which is output
from IC101 is used as the sweep pulse for the electronic shut-
ter.
VMSUB
9
3-level
OSUB 10
VL 5
VL 27
2-level
OV2 24
2-level
OV4 23
2-level
OV6 21
VM 8
3-level
OV1 20
RESET 28
Level
SUBCNT 1
conversion
VDC 3
Level
32
CH1
conversion
Level
V1 33
conversion
Level
V6 31
conversion
Level
V4 30
conversion
Level
V2 29
conversion
Level
V5R 37
conversion
Level
V5L 38
conversion
Level
35
V3R
conversion
Level
V3L 36
conversion
Level
34
V1S
conversion
Fig. 1-3. IC901 Block Diagram
4. IC905 (H Driver, CDS, AGC and A/D converter)
IC905 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
H1, H2, H3, H4, HL and RG are generated inside, and output
to CCD.
The video signal which is output from the CCD is input to pin
(25) of IC905. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the VGA (VGA: Variable Gain Amplifier). It is con-
verted internally into a small-amplitude actuating signal
(LVDS), and is then input to IC101. The gain of the VGA am-
plifier is controlled by pins (32), (33) and (34) using serial
7
VHH
signals which is output from IC101.
2-level
16 OV5R
2-level
15
OV5L
2-level
18
OV3R
2-level
17
OV3L
2-level
19 OV1S
25 VM
3-level
12
OV5A
3-level
11
OV5B
1.8V OUTPUT
3-level
14
OV3A
3-level
13 OV3B
6 VH
26
VH
4 GND
Level
41
CH2
conversion
Level
40 V3
conversion
Level
39 CH4
conversion
Level
44 CH3
conversion
Level
43
V5
conversion
Level
42 CH5
conversion
Level
2 SUB
conversion
– 4 –
6~42 dB
-3, 0, +3, +6dB
CDS VGA
CCDIN
3V INPUT
LDO
REG
INTERNAL
CLOCKS
RG
PRECISION
HORIZONTAL
HL TIMING
DRIVERS
4
GENERATOR
H1 TO H4
SYNC
GENERATOR
HD
GP01 GP02
Fig. 1-4. IC905 Block Diagram
REFT REFB
AD9971
VREF
TCLKP
TCLKN
12-BIT
REDUCED
ADC
RANGE
DOUT0P
LVDS DOUT0N
OUTPUT
DOUT1P
CLAMP
DOUT1N
SL
INTERNAL
SCK
REGISTERS
SDATA
VD CLI