Sony STR-DA2000ES Service Manual page 85

• DIGITAL BOARD IC2121 LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No. Pin Name
1 DISEL
2
DOUT
3
DIN0
4
DIN1
5 DIN2
6
DGND
7
DVDD
8
R
9 VIN
10
LPF
11
AVDD
12
AGND
13
CKOUT
14
BCK
15 LRCK
16 DATAO
17 XSTATE
18 DGND
19 DVDD
20 XMCK
21 XOUT
22 XIN
23 EMPHA
24 AUDIO
25 CSFLAG
26, 27
F0/P0/C0, F1/P1/C1
28
F2/P2/C2
29
F3/P3/C3
30 DVDD
31 DGND
32 AUTO
33 BPSYNC
34 ERROR
35 DO
36 DI
37 CE
38 CLK
39 XSEL
40, 41 MODE0, MODE1
42 DGND
43 DVDD
44, 45
DOSEL0, DOSEL1
46 CKSEL0
47 CKSEL1
48 XMODE
I/O
I Selection signal input terminal of data input terminal Fixed at "L" in this set
O
Digital data output to the external output terminal
I
Digital data input from the external input terminal
I
Digital data input from the external input terminal Not used
I Digital data input from the external input terminal
—
Ground terminal (for digital system)
—
Power supply terminal (+3.3V) (for digital system)
I
Input terminal for VCO gain control
I Input terminal for VCO free-run frequency setting
O
PLL loop filter setting terminal
—
Power supply terminal (+3.3V) (for analog system)
—
Ground terminal (for analog system)
Audio clock (12.288 MHz) signal output to the PCM/PWM processor, DC cut digital filter, A/D
O
converter, DSP and GPR
O
Bit clock signal (2.8224 MHz) output to the A/D converter and DSP
O
L/R sampling clock signal (44.1 kHz) output to the A/D converter and DSP
O
Audio serial data output to the DSP and main system controller
O Source clock selection monitor output to the main system controller
—
Ground terminal (for digital system)
—
Power supply terminal (+3.3V) (for digital system)
O
System clock signal (12.288 MHz) output to the A/D converter
O System clock output terminal (12.288 MHz) Not used
I
System clock input terminal (12.288 MHz)
O
Channel status emphasis information output terminal Not used
O
Channel status bit 1 output to the DSP
O Channel status head 40 bit renewal flag output terminal Not used
O
Output terminal of input frequency calculation result Not used
O
Frequency selection signal output terminal
O
Output terminal of input frequency calculation result Not used
— Power supply terminal (+3.3V) (for digital system)
—
Ground terminal (for digital system)
O
Not used
O
Non-PCM burst preamble sync signal output terminal Not used
O PLL lock error signal and data error flag output to the DSP and main system controller
O
Read data output to the main system controller
I
Write data input from the main system controller
I
Chip enable signal input from the main system controller
I Clock signal input from the main system controller
I
Selection signal input terminal of crystal oscillator frequency Fixed at "H" in this set
I
Mode setting terminal Fixed at "L" in this set
—
Ground terminal (for digital system)
— Power supply terminal (+3.3V) (for digital system)
I
Output data format selection signal input terminal Fixed at "L" in this set
I
Output clock selection signal input terminal Fixed at "L" in this set
I
Output clock selection signal input from the main system controller
I System reset signal input from the main system controller "L": reset
STR-DA2000ES/DB2000
Description
85