NEC VT440 Service Manual page 78

3. I/O PWB block
3-1 RGB OUT circuit
The RGB video signal input entered in Pin 15 of the Mini D-SUB is amplified at the 6dB amplifier (IC4000;
AD8013AR) so that it attains 1Vp-p at the time of 75Ω termination.
The H Sync output is generated through the buffer circuit (Q4000 to Q4002).
The V Sync output is in the THROUGH OUT.
3-2 Plug & Play
The V Sync terminal of Pin 15 of the Mini D-SUB and the serial terminal of Pins 12 and 15 are connected
to the Plug & Play IC (IC4001: 12LC21T) so that the projector can be detected at the PC.
4. MAIN PWB block
4-1 Video signal processor block
The composite video signal passes through the 6dB amplifier (IC1100; MM1031XM) and the low-pass
filter (FL1113), and enters Pin 41 of the video decode IC (IC1104: CXA2139S) at 1Vp-p. The NTSC and
PAL signals are led to the IC's internal SW and 6dB amplifier, and the resultant output is fed to Pin 6. The
signals are further sent to the 3-line Y/C separator circuit (IC1101: TC9090AF). The signals from Y/C
separation are returned again to the video decode IC.
The composite SECAM signal and the B/W signal do not pass through the 3-line Y/C separator circuit. The
composite SECAM signal is processed for Y/C separation by the BPF & TRAP that is incorporated in the
video decode IC.
The SF video input signal is directly entered in the video decode IC.
The result of discrimination for the color system, vertical frequency, etc., to be conducted at the video
decode IC is supervised by the CPU through the I2C bus. According to this result, the CPU controls the 3-
line Y/C separator IC and the video decoder at the appropriate setting values through the I2C bus.
In the video decode IC, the sharpness control and the compensation for the phase in conjunction with the
chroma output signal are carried out for Signal Y. The signal decoded (decoding angle = 90ÅB) to the Y/
chroma in the video decode IC is entered in the A/D converter IC (IC3401: CXA3506R).
The sync signal contained in the Y signal selected by the switch of the video decode IC is sent as the H·V
timing pulses to the sync signal changeover block (IC3301: YAMAG) at the next stage, through the hori-
zontal and vertical sync separator circuit in the IC, the copy guard signal mask circuit, the AFC circuit, IC's
external mono-multi circuit, etc.
4-2 Sync signal processor block (Mini D-SUB 15-pin input)
The sync signal input entered in Pin 15 of the Mini D-SUB is sent to the amplitude limiter circuit. In this
amplitude limiter circuit, the H/V sync signal limited to 0.6Vp-p is applied to the sync signal processor IC
(IC1006: M52347FP).
In order to cope with the sync attenuation signals, the Sync on Green signal input is entered in the sync
signal processor IC via the Sync chip clamp circuit and the AMP circuit. The DVD signal only is entered in
Pin 43 of the video decode IC via IC1001, so that sync processing is conducted in the same manner as for
the video signals.
In the sync signal processor IC, the following processing is carried out:
• Discrimination of the presence of H/V Sync
• Discrimination of the polarity of H/V Sync
• Sync separation for the composite Sync
• Sync separation for the G-Sync
• Generation of clamp pulses
• H/V Sync output
The result of discrimination is read out at the serial D/A (IC1003: CXA1315) and sent to the CPU. The H/
V Sync output is sent to the Sync signal changeover block (IC3301: YAMAG). After the completion of
output synchronization and selection for the video decode IC, the H sync signal is sent to the A/D con-
verter IC (IC3401: CXA3506R) and the V sync signal is sent to the signal processor IC (IC3502: En-
deavor).
CIRCUIT DESCRIPTION
6-5