Omron SYSMAC C20P Operation Manual
  1. Manuals
  2. Brands
  3. Omron Manuals
  4. Computer Hardware
  5. SYSMAC C20P
  6. Operation manual

Omron SYSMAC C20P Operation Manual

Sysmac programmable controllers
Hide thumbs Also See for SYSMAC C20P:
Table of Contents

Advertisement

Quick Links

See also: Installation Manual
Cat. No. W168-E1-1B
SYSMAC
Programmable Controllers
C20P/C28P/C40P/C60P

Advertisement

Table of Contents
loading

Related Manuals for Omron SYSMAC C20P

Summary of Contents for Omron SYSMAC C20P

  • Page 1 Cat. No. W168-E1-1B SYSMAC Programmable Controllers C20P/C28P/C40P/C60P...
  • Page 2 P–type Programmable Controllers OPERATION MANUAL Revised January 1997...
  • Page 3 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high–quality products, the information contained in this manual is subject to change without notice.

  • Page 4: About This Manual

    It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the P-types and a table of other manuals available to use with this manual for special PC applications are also provided.

  • Page 5: Table Of Contents

    1–4 OMRON Product Terminology ........
  • Page 6 Table of contents 4–4 Controlling Bit Status ..........4–4–1 OUT and OUT NOT .
  • Page 7 Table of contents SECTION 7 – Program Input, Debugging and Execution ... . . 7–1 Introduction ............7–2 Converting to Mnemonic Code .

  • Page 8: Precautions

    PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the PC. You must read this section and understand the information contained before attempting to set up or operate a PC system. Intended Audience .

  • Page 9: Intended Audience

    It is extreme important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the abovementioned applications.

  • Page 10: Application Precautions

    Application Precautions Caution The operating environment of the PC System can have a large effect on the lon- gevity and reliability of the system. Improper operating environments can lead to malfunction, failure, and other unforeseeable problems with the PC System. Be sure that the operating environment is within the specified conditions at installa- tion and remains within the specified conditions during the life of the system.

  • Page 11: Section 1 - Background

    1–4 OMRON Product Terminology ........

  • Page 12: Introduction

    Relay vs. PC Terminology The terminology used throughout this manual is somewhat different from re- lay terminology, but the concepts are the same. The following table shows the relationship between relay terms and the PC terms used for OMRON PCs. Relay term...

  • Page 13: Pc Terminology

    Section 1–3 PC Terminology Actually there is not a total equivalence between these terms, because the term condition is used only to describe ladder diagram programs in general and is specifically equivalent to one of certain basic instructions. The terms input and output are not used in programming per se, except in reference to I/O bits that are assigned to input and output signals coming into and leaving the PC.

  • Page 14: Omron Product Terminology

    OMRON products are divided into several functional groups that have ge- neric names. A ppendix A Standard Models list products by these groups. The term Unit is used to refer to all OMRON PC products, depending on the context. The largest group of OMRON products is I/O Units. I/O Units come in a vari- ety of point quantities and specifications.
  • Page 15 Section 1–5 Overview of PC Operation Control System Design Designing the Control System is the first step in automating any process. A PC can be programmed and operated only after the overall Control System is fully understood. Designing the Control System requires a thorough under- standing of the system that is to be controlled.

  • Page 16: Peripheral Devices

    PC program or to interface the PC to external devices to output the program or memory area data. Model numbers for all devices listed below are provided in Appendix A Standard Models . OMRON product names have been placed in bold when introduced in the following descrip- tions.

  • Page 17: Available Manuals

    Section 1–7 Available Manuals 1–7 Available Manuals The following table lists other manuals that may be required to program and/ or operate the P-type PCs. Operation Manuals and/or Operation Guides are also provided with individual Units and are required for wiring and other specifications.

  • Page 18: Section 2 - Hardware Considerations

    SECTION 2 Hardware Considerations 2–1 Introduction ............2–2 Indicators .

  • Page 19: Introduction

    PC Configuration The Units from which P-type PCs can be built are shown below. Unit type Name Words Inputs Outputs occupied provided provided C20P 12 points 8 points C28P 16 points 12 points C40P 24 points 16 points C60P 32 points...

  • Page 20: Section 3 - Memory Areas

    SECTION 3 Memory Areas 3–1 Introduction ............3–2 Data Area Structure .

  • Page 21: Introduction

    Section 3–2 Data Area Structure 3–1 Introduction Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally ac- cessible by the user for use in programming are classified as data areas.
  • Page 22 Section 3–2 Data Area Structure An actual data location within any data area but the TC area is designated by its address. The address designates the bit and/or word within the area where the desired data is located. The TR area consists of individual bits used to store execution conditions at branching points in ladder diagrams.
  • Page 23 Section 3–2 Data Area Structure Data Structure Word data input as decimal values is stored in binary-coded decimal (BCD) code; word data input as hexadecimal is stored in binary form. Because each word contains 16 bits, each four bits of a word represents one digit: either a hexadecimal digit equivalent numerically to the binary bits or decimal.

  • Page 24: Ir Area

    Section 3–3 IR Area There are instructions provided to convert data in either direction between BCD and hexadecimal. Refer to 5–15 Data Conversion for details. Tables of binary equivalents to hexadecimal and BCD digits are provided in the appen- dices for reference. Decimal Points Decimal points are also not stored directly in memory, although some of the parameters contained in data areas have assumed decimal points.
  • Page 25 Section 3–3 IR Area tions as required to achieve effective and proper control. They cannot be used in instructions that control bit status, e.g., the Output, Differentiation Up, and Keep instructions. Output Bit Usage Output bits are used to output program execution results and can be used in any order in programming.
  • Page 26 Section 3–3 IR Area I/O Bits Available in CPUs The following table shows which bits can be used as I/O bits in each of the P-type CPUs. Bits in the shaded areas can be used as work bits but not as output bits.
  • Page 27 Output bits Model Input bits Output bits IR (n + 1) IR (n+1) IR (n + 6) IR (n + 6) C20P C16P Input Cannot be used IR (n+1) IR (n + 6) IR (n + 1) IR (n + 6)
  • Page 28 Section 3–3 IR Area I/O Bits Available in Special The following table shows which bits are allocated to each of the Special I/O I/O Units Units. Bits in the shaded areas can be used as work bits but not as output bits.
  • Page 29 C40P or C60P CPU or Input Output Input Output Expansion I/O Unit C4K/C16P C4K or C16P Expansion I/O Unit Input Output C20P/C28P/TU/AN/LU C20P Expansion I/O Unit, C28P Expansion I/O Unit, Input Output Analog Timer Unit, Analog I/O Unit, or I/O Link Unit...
  • Page 30 IR Area IR 00 IR 05 IR 01 IR 06 IR 02 IR 07 IR 03 IR 08 IR 04 IR 09 C4K/C16P C4K/C16P C4K/C16P C4K/C16P C20P/C28P Input Output Input Output Input Output Input Output Input Output C20P/C28P/TU/AN/LU Input Output C4K/C16P...
  • Page 31 Section 3–3 IR Area IR 00 IR 05 IR 01 IR 06 IR 02 IR 07 IR 03 IR 08 IR 04 IR 09 C4K/C16P C4K/C16P C20P/C28P C20P/C28P/TU/AN/LU C20P/C28P/TU/AN/LU Input Output Input Output Input Output Input Output Input Output C20P/C28P/TU/AN/LU...
  • Page 32 IR 03 IR 08 IR 04 IR 09 C4K/C16P C4K/C16P C4K/C16P C40P/C60P Input Output Input Output Input Output Input Output Input Output C20P/C28P/TU/AN/LU Input Output C4K/C16P C20P/C28P/TU/AN/LU Input Output Input Output C20P/C28P/TU/AN/LU Input Output C40P/C60P Input Output Input Output C4K/C16P...

  • Page 33: Sr Area

    Section 3–4 SR Area 3–4 SR Area The SR area contains flags and control bits used for monitoring system op- eration, accessing clock pulses, and signalling errors. SR area word ad- dresses range from 18 through 19; bit addresses, from 1808 through 1907. The following table lists the functions of SR area flags and control bits.

  • Page 34: Error Flag Er

    Section 3–4 SR Area These clock pulse bits are often used with counter instructions to create tim- ers. Refer to 5–11 Timer and Counter Instructions for an example of this. Pulse width 0.1 s 0.2 s 1.0 s 1900 1901 1902 SR 1900 SR 1901...

  • Page 35: Dm Area

    Section 3–7 TC Area SR 1906 turns ON when the result of a comparison shows two operands to Equal Flag, EQ be equal or when the result of an arithmetic operation is zero. Less Than Flag, LE SR 1907 turns ON when the result of a comparison shows the second of two 4-digit operands to be less than the first.

  • Page 36: Tr Area

    Section 3–8 TR Area TC numbers are also used to access the SV of timers and counters from a Programming Device. The procedures for doing so from the Programming Console are provided in 7–8 Monitoring Operation and Modifying Data. The TC area retains the SVs of both timers and counters during power inter- ruptions.

  • Page 37: Section 4 - Programming

    SECTION 4 Programming 4–1 Introduction ............4–2 Instruction Terminology .

  • Page 38: Introduction

    Section 4–3 The Ladder Diagram 4–1 Introduction This section explains the basic steps and concepts involved in programming and introduces the instructions used to build the basic structure of the ladder diagram and control its execution. The entire set of instructions used in pro- gramming is described in Section 5 Instruction Set .

  • Page 39: Basic Terms

    Section 4–3 The Ladder Diagram branching lines, instruction lines. Along the instruction lines are placed condi- tions that lead to other instructions on the right side. The logical combinations of these conditions determine when and how the instructions at the right are executed.

  • Page 40: Ladder Instructions

    Section 4–3 The Ladder Diagram the instruction is executed. This condition, which is either ON or OFF, is called the execution condition for the instruction. All instructions except for LOAD instructions have execution conditions. Operand Bits The operands designated for any of the ladder instructions can be any bit in the IR, SR, HR or TC area.

  • Page 41: Logic Block Instructions

    Section 4–3 The Ladder Diagram Actually, AND instructions can be considered individually in series, each of which would take the logical AND between the execution condition (i.e., the sum of all conditions up to that point) and the status of the AND instruction’s operand bit.

  • Page 42: Branching Instruction Lines

    Section 4–3 The Ladder Diagram AND Load instruction logically ANDs the execution conditions produced by two logic blocks. The OR Load instruction logically ORs the execution condi- tions produced by two logic blocks. AND Load Although simple in appearance, the diagram below requires an AND Load instruction.
  • Page 43 Section 4–3 The Ladder Diagram serving the previous condition. The following diagrams illustrate this. In both diagrams, instruction 1 is executed before returning to the branching point and moving on to the branch line leading to instruction 2. Branching point 0000 Instruction 1 0002...
  • Page 44 Section 4–3 The Ladder Diagram accordingly. The execution condition that was stored at the branching point is then loaded back in (a Load instruction with TR 0 as the operand) and in- struction 2 is executed accordingly. The following example shows an application using two TR bits. TR 0 TR 1 0000...
  • Page 45 Section 4–3 The Ladder Diagram 0000 0003 Instruction 1 TR 0 0001 0002 0004 Instruction 2 0001 0002 0003 Instruction 1 0000 0001 0004 Instruction 2 Note TR bits are only used when programming using mnemonic code and are not necessary when inputting ladder diagrams directly, as is possible from a GPC.
  • Page 46 Section 4–3 The Ladder Diagram Clear instructions would not affect execution. If 0000 is OFF, the Interlock instruction would produce an OFF execution condition for instructions 1 and 2 and then execution would continue with the instruction line following the Interlock Clear instruction.

  • Page 47: Jumps

    Section 4–3 The Ladder Diagram It’s interesting to notice that if any instructions are added to an interlocked section of a diagram, they in essence branch from the branching point where the Interlock instruction is located, regardless of whether they are drawn that way or whether they are drawn connected directly to the bus bar.

  • Page 48: Controlling Bit Status

    Section 4–4 Controlling Bit Status 0000 JMP(04) 0001 Instruction 1 0002 Instruction 2 JME(05) Diagram B: Corrected with a Jump Execution of programs containing multiple Jump instructions for one Jump End instruction resembles that of similar interlocked sections. The following diagram is the same as that used for the interlock example above, except redrawn with jumps.

  • Page 49: Differentiate Up And Differentiate Down

    Section 4–4 Controlling Bit Status tion is ON and will be turned OFF as long as the execution condition is OFF. With the OUT NOT instruction, the operand bit will be turned ON as long as the execution condition is OFF and turned OFF as long as the execution con- dition is ON.

  • Page 50: Self-Maintaining Bits

    Section 4–5 The End Instruction In the following example, HR 000 will be turned ON when 0002 is ON and 0003 is OFF. HR 000 will then remain ON until either 0004 or 0005 turns ON. 0002 0003 KEEP(11) HR 000 S: set input 0004 R: reset input...

  • Page 51: Programming Precautions

    Section 4–6 Programming Precautions If there is no End instruction anywhere in the program, the program will not be executed at all. 4–6 Programming Precautions The number of conditions that can be used in series or parallel is unlimited. Therefore, use as many conditions as required to draw a clear diagram. Al- though very complicated diagrams can be drawn with instruction lines almost forming mazes, there must not be any conditions on instruction lines running vertically between two other instruction lines.

  • Page 52: Program Execution

    Section 4–7 Program Execution tion of the first of the pair. Conditions should not be placed on the instruction lines leading to these instructions. Refer to Section 5 Instruction Set for de- tails. When drawing ladder diagrams, it is important to keep in mind the number of instructions that will be required to input it.

  • Page 53: Section 5 - Instruction Set

    SECTION 5 Instruction Set 5–1 Introduction ............5–2 Notation .

  • Page 54: Introduction

    Section 5–3 Instruction Format 5–1 Introduction The P-type PCs have large programming instruction sets that allow for easy programming of complicated control processes. This section explains each instruction individually and provides the ladder diagram symbol, data areas, and flags used with each. Basic application examples are also provided as required in describing the instructions.

  • Page 55: Data Areas, Definer Values, And Flags

    Section 5–5 Ladder Diagram Instructions 5–4 Data Areas, Definer Values, and Flags Each instruction is introduced with the ladder diagram symbol(s), the data areas that can be used with any operand(s), and the values that can be used for definers. With the data areas is also specified the operand names and the type of data required for each operand (i.e., word or bit and, for words, hexa- decimal or BCD).

  • Page 56: Load, Load Not, And, And Not, Or, And Or Not

    Section 5–5 Ladder Diagram Instructions 5–5–1 Load, Load NOT, AND, AND NOT, OR, and OR NOT Load – LD Ladder Symbol Operand Data Areas B: Bit IR, SR, HR, TC, TR Load NOT – LD NOT Ladder Symbol Operand Data Areas B: Bit IR, SR, HR, TC, TR AND –...

  • Page 57: And Load And Or Load

    Section 5–6 Bit Control Instructions 5–5–2 AND Load and OR Load AND Load – AND LD 0000 0002 Ladder Symbol 0001 0003 OR Load – OR LD 0000 0001 Ladder Symbol 0002 0003 Description When the above instructions are combined into blocks that cannot be logi- cally combined using only OR and AND operations, AND LD and OR LD are used.

  • Page 58: Differentiate Up And Down - Difu(13) And Difd(14

    Section 5–6 Bit Control Instructions OUT turns ON the designated bit for a ON execution condition, and turns OFF the designated bit for an OFF execution condition. OUT with a TR bit appears at a branching point rather than at the end of an instruction line. Re- fer to 4–3–4 Branching Instruction Lines for details.

  • Page 59: Keep - Keep(11)

    Section 5–6 Bit Control Instructions DIFU(13) and DIFD(14) operation can be tricky when used in programming between IL and ILC, between JMP and JME, or in subroutines. Refer to 5–7 Interlock and Interlock Clear – IL(02) and ILC(03) and 5–8 Jump and Jump End –...
  • Page 60 Section 5–6 Bit Control Instructions S execution condition R execution condition Status of B Notice that KEEP(11) operates like a self-maintaining bit. The following two diagrams would function identically, though the one using KEEP(11) requires one less instruction to program and would maintain status even in an inter- locked program section.

  • Page 61: Interlock And Interlock Clear - Il(02) And Ilc(03)

    Section 5–7 Interlock and Interlock Clear 0002 KEEP HR 000 0003 Indicates emergency situation 0004 Reset input 0005 HR 000 Activates warning 0500 display KEEP(11) can also be combined with TIM to produce delays in turning bits ON and OFF. Refer to 5–11–1 Timer – TIM for details. 5–7 Interlock and Interlock Clear –...
  • Page 62 Section 5–7 Interlock and Interlock Clear cution condition for the IL(02) is OFF. When DIFU(13) or DIFD(14) is ex- ecuted in an interlocked section immediately after the execution condition for the IL(02) has gone ON, the execution condition for the DIFU(13) or DIFD(14) will be compared to the execution condition that existed before the interlock became effective (i.e., before the interlock condition for IL(02) went OFF).

  • Page 63: Jump And Jump End - Jmp(04) And Jme(05)

    Section 5–8 Jump and Jump End When the execution condition for the first IL(02) is OFF, TIM 11 will be reset to 1.5 s, CNT 01 will not be changed, and 0502 will be turned OFF. When the execution condition for the first IL(02) is ON and the execution condition for the second IL(02) is OFF, TIM 11 will be executed according to the status of 0001, CNT 01 will not be changed, and 0502 will be turned OFF.

  • Page 64: End - End(01)

    Section 5–11 Timer and Counter Instructions 5–9 End – END(01) Ladder Symbol END(01) Description END(01) is required as the last instruction in any program. No instruction written after END(01) will be executed. END(01) can be placed anywhere in the program to execute all instructions up to that point, as is sometimes done to debug a program, but it must be removed to execute the remainder of the program.

  • Page 65: 5-11-1 Timer - Tim

    Section 5–11 Timer and Counter Instructions used to define that timer or counter to access the memory location that holds the PV. Note that “TIM 00” is used to designate the Timer instruction defined with TC number 00, to designate the Completion Flag for this timer, and to designate the PV of this timer.
  • Page 66 Section 5–11 Timer and Counter Instructions Execution condition Completion Flag Precautions Timers in interlocked program sections are reset when the execution condi- tion for IL(02) is OFF. Power interruptions also reset timers. If a timer that is not reset under these conditions is desired, SR area clock pulse bits can be counted to produce timers using CNT.
  • Page 67 Section 5–11 Timer and Counter Instructions In this example, 0200 will be turned ON 30 minutes after 0000 goes ON. TIM can also be combined with CNT or CNT can be used to count SR area clock pulse bits to produce longer timers. An example is provided in 5–11–4 Counter –...
  • Page 68 Section 5–11 Timer and Counter Instructions 1000 0000 1000 TIM 01 1000 TIM 0100 1.5 s 1000 TIM 01 0204 0000 0204 1.5 s 1.5 s Example 5: Bits can be programmed to turn ON and OFF at a regular interval while a Flicker Bits designated execution condition is ON by using TIM twice.

  • Page 69: High-Speed Timer - Timh(15)

    Section 5–11 Timer and Counter Instructions 5–11–2 High-speed Timer – TIMH(15) Definer Values N: TC number Ladder Symbol # (00 though 47 ) TIMH(15) Operand Data Areas SV: Set value (word, BCD) IR, HR, # Limitations SV may be between 00.00 and 99.99 seconds. The decimal point of SV is not input.
  • Page 70 Section 5–11 Timer and Counter Instructions Input word Output word Time Expired Flag Start Control Bit Time Expired Flag Start Control Bit Time Expired Flag Start Control Bit Time Expired Flag Start Control Bit Pause Control Bit Pause Control Bit Pause Control Bit Pause Control Bit Range Bits...
  • Page 71 Section 5–11 Timer and Counter Instructions Unit Input word Output word Analog Timer Unit All four time’s are used. Times for two of them are adjusted on the variable resistors provided on the Analog Timer Unit. The other two times are ad- justed using external resistors.

  • Page 72: 5-11-4 Counter - Cnt

    Section 5–11 Timer and Counter Instructions 0015 0606 Used to inhibit operation of T and T 0607 Start Control Bit 0002 started. 0600 Time Expired Flag 0100 0500 turned ON when time for T expires. 0500 Start Control Bit 0003 started.
  • Page 73 Section 5–11 Timer and Counter Instructions tion for CP and the execution condition was OFF for the last execution. If the execution condition has not changed or has changed from ON to OFF, the PV of CNT will not be changed. Counter is turned ON when the PV reaches zero and will remain ON until the counter is reset.
  • Page 74 Section 5–11 Timer and Counter Instructions Example 2: Counters that can count past 9,999 can be programmed by using one CNT to Extended Counter count the number of times another CNT has reached zero from SV. In the following example, 0000 is used to control when CNT 01 operates and CNT 01, when 0000 is ON, counts down the number of OFF to ON changes in 0001.

  • Page 75: Reversible Counter - Cntr(12)

    Section 5–11 Timer and Counter Instructions 0000 TIM 01 CNT 02 5.0 s 0100 TIM 01 CNT 02 0001 #0100 CNT 00 0200 In the following example, CNT 01 counts the number of times the 1-second clock pulse bit (1902) goes from OFF to ON. Here again, 0000 is used to control when CNT is operating.

  • Page 76: High-Speed Counter - Hdm(98)

    Section 5–11 Timer and Counter Instructions was OFF for II for the last execution. The present value (PV) will be decre- mented by one whenever CNTR(12) is executed with an ON execution condi- tion for DI and the execution condition was OFF for DI for the last execution. If OFF to ON changes have occurred in both II and DI since the last execu- tion, the PV will not be changed.
  • Page 77 Section 5–11 Timer and Counter Instructions If the time it takes to count through some range is less than the scan time of the CPU, the high-speed counter may count past between scans and thus the output bit for this range may not be turned ON. Counting Time Lower Limit Upper Limit...
  • Page 78 Section 5–11 Timer and Counter Instructions Hard Reset To use the hard reset, turn pins 7 and 8 ON. In this mode, input 0001 is the reset input. When it is turned ON, the present value in the high-speed count- er buffer is reset to “0000”.
  • Page 79 Section 5–11 Timer and Counter Instructions Upper and Lower Limit The following table shows the upper and lower limits that need to be set in Setting DM 32 through DM 63. In this table, “S” denotes the present value of counter 47 and R is the results word.
  • Page 80 Section 5–11 Timer and Counter Instructions 1813 (normally ON) MOV(21) #0200 DM 32 MOV(21) #1500 DM 33 Transfers preset value to DM 32 to MOV(21) #0600 DM 34 MOV(21) #2000 DM 35 0002 (start input) HDM(98) Corresponding result word is 05 Start input 0002 Count input 0000 1500...
  • Page 81 Section 5–11 Timer and Counter Instructions 1813 (normally ON) MOV(21) “S1” DM 32 Transfers limit values S1 to S32 to DM. MOV(21) Output thru HR 0 “S2” DM 33 MOV(21) “S32” DM 35 0002 HDM(98) HR 0 1813 (normally ON) MOV(21) “S33”...
  • Page 82 Section 5–11 Timer and Counter Instructions S32 and S33 so that there is a value difference equivalent to the time lag from points A to B. For example, set the value of S32 to 2,000 and that of S33 to 2,010. More than 16 output bits may be obtained using CMP.
  • Page 83 Section 5–11 Timer and Counter Instructions the high-speed counter, programming is easier with CNTR since an ordinary counter is decrementing. 1813 (normally ON) MOV(21) #0000 DM 32 MOV(21) #5000 DM 33 0002 (start input) HDM(98) HR 0 CNT 47 CNTR(12) 1814 (normally OFF) #9999 1810 (turns On for 1 scan upon hard reset)
  • Page 84 Section 5–11 Timer and Counter Instructions Reflective photoelectric switch PH1 (0002) Motor 2 (M2) Rear limit switch for Rotary encoder E6A pusher LS1 (0003) (0000) Fixed stopper Pusher Front limit switch for Packages pusher LS2 (0004) Upper limit switch for stopper LS3 (0005) Moving stopper Motor 1 (M1) Lower limit switch for stopper LS4 (0006)

  • Page 85: 5-12 Data Shifting

    Section 5–12 Data Shifting 1813 (normally ON) MOV(21) #0905 DM 32 MOV(21) #1150 DM 33 Transfer limit values MOV(21) #1450 DM 34 MOV(21) #1550 DM 35 1815 Resets counter 1807 upon power application or at stopper 0005 operation 0002 Counts pulses HDM(60) from encoder only when PH1...

  • Page 86: Shift Register - Sft(10)

    Section 5–12 Data Shifting condition. SFTR(84) creates a reversible shift register that is controlled through the bits in a control word. WSFT(16) creates a multiple-word register that shifts by word. 5–12–1 Shift Register – SFT(10) Ladder Symbol Operand Data Areas St : Starting word SFT(10) IR, HR...
  • Page 87 Section 5–12 Data Shifting Example 1: The following example uses the 1-second clock pulse bit (1902) to so that the Basic Application execution condition produced by 0005 is shifted into a 3-word register be- tween 10 and 12 every second. 0005 SFT(10) 1902...

  • Page 88: Word Shift - Wsft(16)

    Section 5–12 Data Shifting Sensor (0001) Pusher (0500) Sensor (0002) Rotary Encoder (0000) Chute 0001 SFT(10) 0000 HR 0 0003 HR 1 HR 003 0500 0002 0500 HR 003 5–12–2 Word Shift – WSFT(16) Ladder Symbols Operand Data Areas St : Start word WSFT(16) IR, DM, HR E : End word...

  • Page 89: 5-13 Data Movement

    Section 5–13 Data Movement St + 1 Lost 0000 St + 1 Flags St and E are not in the same data area. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) 5–13 Data Movement This section describes the instructions used for moving data between differ- ent addresses in data areas.

  • Page 90: Move Not - Mvn(22)

    Section 5–14 Data Comparison 5–13–2 Move NOT – MVN(22) Ladder Symbol Operand Data Areas S : Source word MVN(22) IR, SR, DM, HR, TC, # D : Destination word IR, DM, HR Description When the execution condition is OFF, MVN(22) is not executed and the next instruction is moved to.
  • Page 91 Section 5–14 Data Comparison Precautions Placing other instructions between CMP(20) and accessing EQ, LE, and GR may change the status of these flags. Be sure to access them before the de- sired status is changed. Flags ON if Cp1 equals Cp2. ON if Cp1 is less than Cp2.

  • Page 92: 5-15 Data Conversion

    Section 5–15 Data Conversion 0000 TIM 10 0500 s. CMP(20) TIM 10 #4000 1907 Output at 0200 100 s. 0200 CMP(20) TIM 10 #3000 1907 Output at 0201 200 s. 0201 CMP(20) TIM 10 #2000 1907 Output at 0202 300 s. TIM 10 Output at 0204...

  • Page 93: Binary To Bcd - Bcd(24)

    Section 5–15 Data Conversion Flags The content S is not BCD ON when 0000 is placed in R. 5–15–2 Binary to BCD – BCD(24) Ladder Symbol Operand Data Areas S : Source word (binary) BCD(24) IR, SR, DM, HR, TC R : Result word IR, DM, HR Limitations...

  • Page 94: Data Conversion

    Section 5–15 Data Conversion The following is an example of a one-digit decode operation from digit num- ber 1 of S, i.e., here Di would be 0001. Bit C (i.e., bit number 12) turned ON. The first digit and the number of digits to be converted are designated in Di. If more digits are designated than remain in S (counting from the designated first digit), the remaining digits will be taken starting back at the beginning of S.

  • Page 95: 16-To-4 Encoder - Dmpx(77)

    Section 5–15 Data Conversion Flags Undefined digit designator, or R plus number of digits exceeds a data area. Example The following program converts three digits of data from DM 20 to bit posi- tions and turns ON the corresponding bits in three consecutive words starting with HR 1.
  • Page 96 Section 5–15 Data Conversion Description When the execution condition is OFF, DMPX(77) is not executed and the next instruction is moved to. When the execution condition is ON, DMPX(77) determines the position of the highest ON bit in S, encodes it into single-digit hexadecimal value corresponding to the bit number of the highest ON bit number, then transfers the hexadecimal value to the specified digit in R.

  • Page 97: 5-16 Bcd Calculations

    Section 5–16 BCD Calculations Di : 0011 Di : 0030 S + 1 S + 1 S + 2 S + 3 Di : 0013 Di : 0032 S + 1 S + 1 S + 2 S + 3 Flags Undefined digit designator, or S plus number of digits exceeds a data area.

  • Page 98: Bcd Add - Add(30)

    Section 5–16 BCD Calculations These instructions change only the content of the words in which results are placed, i.e., the contents of source words are the same before and after exe- cution of any of the BCD calculation instructions. STC(40) and CLC(41), which set and clear the Carry Flag, are included in this group because most of the BCD operations make use of the Carry Flag (CY) in their results.
  • Page 99 Section 5–16 BCD Calculations TR 0 0002 CLC(41) ADD(30) #6103 DM 01 1904 MOV(21) #0001 DM 02 1904 MOV(21) #0000 DM 02 Consecutive ADD(30)s can be used to perform eight-digit BCD addition. By using two ADD(30)s and combining the augend and the addend words of one ADD(30) with those of the other, two 8-digit values can be added.

  • Page 100: Bcd Subtract - Sub(31)

    Section 5–16 BCD Calculations If a carry is generated, SR 1904 (CY) is turned ON and the constant 0001 is transferred to DM 06. If a carry is not generated SR 1904 remains OFF and the constant 0000 is transferred to DM 06. 5–16–2 BCD Subtract –...

  • Page 101: Set Carry - Stc(40)

    Section 5–16 BCD Calculations TR 0 0002 CLC(41) SUB(31) First subtraction DM 01 HR 2 1904 CLC(41) SUB(31) Second subtraction #0000 HR 2 HR 2 1904 HR 300 HR 300 Turned ON to indicate negative result. 5–16–3 Set Carry – STC(40) Set carry is used to set (turn ON) the CY (SR bit 1904) to “1”.

  • Page 102: Section 6 - Program Execution Timing

    SECTION 6 Program Execution Timing 6–1 Introduction ............6–2 Scan Time .

  • Page 103: Introduction

    Section 6–2 Scan Time 6–1 Introduction When writing and debugging a program, the timing of various operations must be considered. Not only is the time required to execute the program and perform other CPU operations important, but also the timing of each sig- nal coming into and leaving the PC must be such that the desired control ac- tion is achieved at the right time.
  • Page 104 Section 6–2 Scan Time Power application Clears IR area and resets all timers Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory Check OK? Sets error flags and lights indicator Services Peripheral Devices ERROR or ALARM ALARM Resets watchdog timer ERROR Executes program...

  • Page 105: Calculating Scan Time

    Section 6–3 Calculating Scan Time Overseeing Watchdog timer set and program 1.26 ms (Fixed) memory and I/O bus checked. Peripheral Device Commands from Program Devices and T = ( 1 + 3 + 4 ) x 0.05. servicing Interface Units processed. T <= 1, execution time = 1 ms.

  • Page 106: Pc With Additional Units

    Section 6–3 Calculating Scan Time The overseeing time is fixed at 1.26 ms. The input/output refresh time would be as follows: 0.29 ms + ( 0.07 ms x N ). As the C20K is provided with only one input and one output word the value of the constant N is 1 (i.e.

  • Page 107: Instruction Execution Times

    Section 6–4 Instruction Execution Times + Peripheral device servicing time + Instruction execution time The overseeing time is fixed at 1.26 ms. The input/output refresh time would be as follows: 0.29 ms + (0.07 ms x N ). As the C40K is provided with only one input and one output word and the C40P Expansion unit contains input and output words the value of the con- stant N is 5.
  • Page 108 Section 6–4 Instruction Execution Times Function Instruction Execution Conditions µ code time( Always LD NOT Always 11.5 Always AND NOT 11.5 Always 11.5 Always OR NOT 11.5 Always AND LD Always OR LD Always When outputting logical ”1” (ON) 17.5 When outputting logical ”0”...

  • Page 109: I/O Response Time

    Section 6–5 I/O Response Time Function Instruction Execution Conditions µ code time( When adding two words When adding a TIM/CNT to a constant 237.5 When subtracting a word from a word 356.5 When subtracting a constant from a TIM/CNT Always Always Always MLPX...
  • Page 110 Section 6–5 I/O Response Time Overseeing CPU reads input signal Scan time Scan time Scan I/O refresh Input signal CPU writes output signal Input ON delay Output ON delay Output signal I/O response time Minimum I/O response time = Input ON delay + Scan time + I/O refresh time + Overseeing time + Output ON delay Maximum I/O Response The PC takes longest to respond when it receives the input signal just after...
  • Page 111 Section 6–5 I/O Response Time Calculation Example The data in the following table would produce the minimum and maximum scan times shown calculated below. Input ON-delay 1.5 ms Scan time 20 ms Input refresh time 0.23 ms Overseeing time 3.0 ms Output ON-delay 15 ms Minimum I/O response time = 1.5 + 20 + 0.23 + 3.0 +15 = 39.73 ms...

  • Page 112: Section 7 - Program Input, Debugging And Execution

    SECTION 7 Program Input, Debugging and Execution 7–1 Introduction ............7–2 Converting to Mnemonic Code .

  • Page 113: Introduction

    Section 7–2 Converting to Mnemonic Code 7–1 Introduction This section provides the procedures for inputting and debugging a program and monitoring and controlling the PC through a Programming Console. The Programming Console is the most commonly used Programming Device for the K-type PCs.

  • Page 114: Logic Block Instructions

    Section 7–2 Converting to Mnemonic Code Address Instruction Data 0005 0006 0000 0005 0505 0001 0006 0002 0505 All instruction lines begin with a LD or LD NOT for the first condition. LD or LD NOT is always used when an instruction line starts from the bus bar. The address of the operand bit for LR (here, 0005) is written into the data column next to LD.
  • Page 115 Section 7–2 Converting to Mnemonic Code To use logic block instructions, the diagram must be divided into logic blocks. Each block is coded using LD to code the first condition, and then AND LD or OR LD is used to logically combine the blocks. With both AND LD and OR LD there are two ways to achieve this.
  • Page 116 Section 7–2 Converting to Mnemonic Code 0000 0001 0501 0002 0003 0004 0005 The first of each pair of conditions is converted to LD with the assigned bit operand and then ANDed with the other condition. The first two blocks can be coded first, followed by OR LD, the last block, and another OR LD, or the three blocks can be coded first followed by two OR LDs.
  • Page 117 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 0000 0001 AND NOT 0001 0002 0002 0003 0003 0004 0201 0005 0004 0006 AND LD — 0007 0501 Although the following diagram is similar to the one above, block b in the dia- gram below cannot be coded without being broken down into two blocks combined with OR LD.
  • Page 118 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 LD NOT 0000 0001 0001 0002 0002 0003 AND NOT 0003 0004 LD NOT 0004 0005 0202 0006 OR LD — 0007 AND LD — 0008 0502 Complicated Diagrams When determining what logic block instructions will be required to code a dia- gram, it is sometimes necessary to break the diagram into large blocks and then continue breaking the large blocks down until logic blocks that can be coded without logic block instructions have been formed.
  • Page 119 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 0000 0001 AND NOT 0001 0002 LD NOT 0002 0003 0003 0004 OR LD — Blocks a1 and a2 0005 0004 0006 0005 0007 0006 0008 0007 0009 OR LD —...
  • Page 120 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 0000 0001 0001 0002 0002 0003 AND NOT 0003 0004 OR LD –– 0005 AND LD –– 0006 LD NOT 0004 0007 0005 0008 OR LD –– 0009 LD NOT 0006 0010 0007...
  • Page 121 Section 7–2 Converting to Mnemonic Code 0000 0001 0002 0505 Block b Block a Block c Block d 0003 0004 0005 0006 0007 Block e Address Instruction Data 0000 0000 0001 0001 0002 0002 0003 0003 0004 0004 0005 0005 0006 0006 0007...
  • Page 122 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 0006 0001 0007 0002 0005 0003 0003 0004 0004 0005 0001 0006 0002 0007 OR LD –– 0008 0000 0009 0505 Our last example may at first appear very complicated but can be coded us- ing only two logic block instructions.

  • Page 123: Coding Other Instructions

    Section 7–2 Converting to Mnemonic Code Address Instruction Data Address Instruction Data 0000 0000 0007 AND NOT 0003 0001 0001 0008 0004 0002 0100 0009 0005 0003 0101 0010 0006 0011 AND LD –– 0004 OR LD –– 0005 0500 0012 0505 0006...
  • Page 124 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 0001 0000 0000 DIFU(13) 1500 0002 0001 0001 0002 0002 0003 DIFU(13) 1500 0100 0200 1500 ADD(30) 0004 0100 0101 0102 1505 #0001 0005 AND NOT 0200 0004 0006 0101 HR 0 0007 AND NOT...
  • Page 125 Section 7–2 Converting to Mnemonic Code Address Instruction Data 0000 0000 0001 0001 0002 0002 0003 0100 0004 AND NOT 0200 0005 0101 0006 AND NOT 0102 0007 AND NOT 1501 0008 OR LD –– 0009 1500 0010 CNTR(12) –– 5000 0011 0012...
  • Page 126 Section 7–2 Converting to Mnemonic Code TR Bits TR bits in a program are used to output (OUT) the execution condition at the branching point and then to load back (LD) the execution condition when it is required after returning to the branch lines. Within any one instruction block, OUT cannot be used with the same TR address.
  • Page 127 Section 7–2 Converting to Mnemonic Code 0000 0001 0002 0500 0003 0501 0502 0005 0503 Address Instruction Data 0000 0000 0001 0002 0001 0003 0004 0002 0005 0500 0006 0007 0003 0008 0501 0009 0010 0502 0011 AND NOT 0005 0012 0503 Interlocks...

  • Page 128: The Programming Console

    Section 7–3 The Programming Console IL(02) 0000 0001 0500 IL(02) 0002 0003 0004 0501 0005 0502 0006 0503 ILC(03) Address Instruction Data 0000 0000 0001 IL(02) –– 0002 0001 0003 0200 0004 0002 0005 IL(02) –– 0006 0003 0007 AND NOT 0004 0008 0201...
  • Page 129 Section 7–3 The Programming Console programming operations. Any Programming Console operation can be can- celled by pressing the CLR key, although the CLR key may have to be pressed two or three times to cancel the operation and clear the display. Yellow Operation Keys The yellow keys are used for writing and correcting programs.

  • Page 130: Pc Modes

    Section 7–3 The Programming Console Pressed before the function code when inputting an instruction via its function code. Pressed to enter SFT (the Shift Register instruction). Input after a ladder instruction to designate an inverse condi- tion. Pressed to enter AND (the AND instruction) or used with NOT to enter AND NOT.

  • Page 131: Preparation For Operation

    Section 7–4 Preparation for Operation MONITOR mode allows you to visually monitor in-progress program execu- tion while controlling I/O status, changing PV (present values) or SV (set val- ues), etc. In MONITOR mode, I/O processing is handled in the same way as in RUN mode.

  • Page 132: Entering The Password

    Section 7–4 Preparation for Operation 1, 2, 3... Confirm that all wiring for the PC has been installed and checked prop- erly. Confirm that a RAM Unit is mounted as the Memory Unit and that the write-protect switch is OFF. Connect the Programming Console to the PC (referring to the Program- ming Console Operation Guide ).

  • Page 133: Clearing Memory

    Section 7–4 Preparation for Operation The beeper will also sound whenever an error occurs during PC operation. Beeper operation for errors is not affected by the above setting. 7–4–2 Clearing Memory Using the Memory Clear operation it is possible to clear all or part of the Pro- gram Memory, and the IR, HR, DM and TC areas.
  • Page 134 Section 7–4 Preparation for Operation Partial Clear It is possible to retain the data in specified areas and/or part of the Program Memory. To retain the data in the HR and TC, and/or DM areas, press the appropriate key after entering REC/RESET. The CNT key is used for the en- tire TC area.

  • Page 135: Inputting, Modifying, And Checking The Program

    Section 7–5 Inputting, Modifying, and Checking the Program 7–5 Inputting, Modifying, and Checking the Program Once a program has been converted to mnemonic code, it is ready to be in- put into the PC and checked. Mnemonic code is keyed into Program Memory addresses from the Programming Console.

  • Page 136: Inputting Or Overwriting Programs

    Section 7–5 Inputting, Modifying, and Checking the Program 7–5–2 Inputting or Overwriting Programs Programs can be input or overwritten only in PROGRAM mode. The same procedure is used to either input a program for the first time or to overwrite a program that already exists. In either case, the current contents of Program Memory are overwritten, i.e., if there is no previous program, the NOP(00) instruction, which will be written at every address, will be overwrit- ten.
  • Page 137 Section 7–5 Inputting, Modifying, and Checking the Program When inputting an SV as a constant, CONT/# is not required; just input the numeric value and press WRITE. To designate a word, press CLR and then input the word address as described above. Designating Instructions The most basic instructions are input using the Programming Console keys provided for them.
  • Page 138 Section 7–5 Inputting, Modifying, and Checking the Program The following error messages may appear when inputting a program. Correct Error Messages the error as indicated and continue with the input operation. The asterisks in the displays shown below will be replaced with numeric data, normally an address, in the actual display.

  • Page 139: Checking The Program

    Section 7–5 Inputting, Modifying, and Checking the Program Message Cause and correction ****REPL ROM An attempt was made to write to ROM or to write-protected RAM. Be sure a RAM Unit is mounted and that its write-pro- tect switch is set to OFF. ****PROG OVER The instruction at the last address in memory is not NOP(00).

  • Page 140: Displaying The Scan Time

    Section 7–5 Inputting, Modifying, and Checking the Program Message Meaning and appropriate response JMP–JME ERR JMP(04) and JME(05) are not used in pairs. Match each JMP(04) to a JME(05). COIL DUPL The same bit is being controlled (i.e., turned ON and/or OFF) by more than one instruction (e.g., OUT, OUT NOT, DIFU(13), DIFD(14), KEEP(11), SFT(10)).

  • Page 141: Program Searches

    Section 7–5 Inputting, Modifying, and Checking the Program gram is being executed. See Section 6 Program Execution Timing for details on the scan time. To display the current average scan time, press CLR then MONTR. The time displayed by this operation is an average scan time. The differences in dis- played values depend on the execution conditions that exist when MONTR is pressed.
  • Page 142 Section 7–5 Inputting, Modifying, and Checking the Program Example: Instruction Searches...

  • Page 143: Inserting And Deleting Instructions

    Section 7–5 Inputting, Modifying, and Checking the Program Bit Search 7–5–6 Inserting and Deleting Instructions In PROGRAM mode, any instruction that is currently displayed can be de- leted or another instruction can be inserted before it. These are not possible in RUN or MONITOR modes.
  • Page 144 Section 7–5 Inputting, Modifying, and Checking the Program Before Insertion Address Instruction Data 0000 0100 0001 0101 0002 0201 0003 AND NOT 0102 0004 OR LD – 0005 0103 0006 AND NOT 0104 0007 0201 0008 END(01) – After Insertion After Deletion Address Instruction...
  • Page 145 Section 7–5 Inputting, Modifying, and Checking the Program Find the address prior to the insertion point Insert the instruction...
  • Page 146 Section 7–5 Inputting, Modifying, and Checking the Program Find the instruction that re- quires dele- tion. Confirm that this is the instruction to be deleted.

  • Page 147: Program Backup And Restore Operations

    Section 7–8 Program Backup and Restore Operations 7–6 Program Backup and Restore Operations Program Memory (UM) can be backed-up on a standard commercially avail- able cassette tape recorder. Any kind of dependable magnetic tape of ade- quate length will suffice. To save a 16K-word program, the tape must be 30 minutes long.

  • Page 148: Restoring Or Comparing Program Memory Data

    Section 7–8 Program Backup and Restore Operations Example Within 5 seconds... Blinking (Recording in progress) Blinking When it comes to END Blinking Stop recording with CLR Saved up to the final address) 7–6–2 Restoring or Comparing Program Memory Data This operation is used to restore Program Memory data from a cassette tape or to compare Program Memory data with the contents on a cassette tape.
  • Page 149 Section 7–8 Program Backup and Restore Operations Key Sequence Example...

  • Page 150: Debugging

    Section 7–6 Debugging 7–7 Debugging After inputting a program and correcting it for syntax errors, it must be exe- cuted and all execution errors must be eliminated. Execution errors include an excessively long scan time, errors in settings for various Units in the PC, and inappropriate control actions, i.e., the program not doing what it is de- signed to do.

  • Page 151: Monitoring Operation And Modifying Data

    Section 7–7 Monitoring Operation and Modifying Data Fatal errors Non-fatal errors All errors have been cleared 7–8 Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or one of the search operations.

  • Page 152: Bit/Digit Monitor

    Section 7–7 Monitoring Operation and Modifying Data 7–8–1 Bit/Digit Monitor The status of any bit or word in any data area can be monitored using the following operation. Although the operation is possible in any mode, ON/OFF status displays will be provided for bits only in MONITOR or RUN mode. The Bit/Digit Monitor operation can be entered either from a cleared display by designating the first bit or word to be monitored or it can be entered from any address in the program by displaying the bit or word address whose...
  • Page 153 Section 7–7 Monitoring Operation and Modifying Data Key Sequence Examples The following examples show various applications of this monitor operation. Program Read then Monitor Indicates the Completion flag is ON...
  • Page 154 Section 7–7 Monitoring Operation and Modifying Data Bit Monitor Word Monitor...

  • Page 155: Force Set/Reset

    Section 7–7 Monitoring Operation and Modifying Data Multiple Address Monitoring 7–8–2 Force Set/Reset When the Bit/Digit Monitor operation is being performed and a bit, timer, or counter address is leftmost on the display, PLAY/SET can be pressed to turn ON the bit, start the timer, or increment the counter and REC/RESET can be pressed to turn OFF the bit or reset the timer or counter.
  • Page 156 Section 7–7 Monitoring Operation and Modifying Data Bit status will remain ON or OFF for only one scan after pressing the key; it will then return to its original status. When timers or counters are reset in MONITOR mode, they will start after one scan. This operation can be used in MONITOR mode to check wiring of outputs from the PC prior to actual program execution.
  • Page 157 Section 7–7 Monitoring Operation and Modifying Data Returns to the original condition after a scan Indicates that the time is up The timer commences after the first scan OUT 0501 is ON after the timer has reached its SV...

  • Page 158: Hexadecimal/Bcd Data Modification

    Section 7–7 Monitoring Operation and Modifying Data 7–8–3 Hexadecimal/BCD Data Modification When the Bit/Digit Monitor operation is being performed and a BCD or hexa- decimal value is leftmost on the display, CHG can be input to change the value. SR words cannot be changed. If a timer or counter is leftmost on the display, the PV will be displayed and will be the value changed.
  • Page 159 Section 7–7 Monitoring Operation and Modifying Data When changing the SV of timers or counters while operation is stopped, use PROGRAM mode and follow the procedure outlined in 7–5–2 Inputting or Overwriting Programs. This operation can be used to change a SV from designation as a constant to a word address designation and visa verse.
  • Page 160 SECTION 8 Troubleshooting 8–1 Introduction ............8–2 Reading and Clearing Errors and Messages .

  • Page 161: Introduction

    Section 8–3 Error Messages 8–1 Introduction The P-type PCs provide self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation.
  • Page 162 Section 8–3 Error Messages Probable cause Possible correction Error and message Watchdog timer has ex- Program scan time is longer Scan time overrun ceeded 100 ms. then desirable. Reduce scan time if possible. Backup battery is miss- Check battery and replace if Battery error ing or it’s voltage has necessary.

  • Page 163: Error Flags

    Section 8–4 Error Flags 8–4 Error Flags The following table lists the flags and other information provided in the SR area that can be used in troubleshooting. Details are provided in 3–4 SR Area. SR Area Address Function 1808 Battery Alarm Flag 1809 Scan Time Error Flag 1903...

  • Page 164: Appendix

    There are four basic sizes of P-type C-series CPU. A CPU can be combined with any of six basic sizes of Expan- sion I/O Unit and/or Analog Timers, Analog I/O Units, or an I/O Link Unit. Analog Timer Unit CPUs Expansion I/O Units C4K–TM C20P–C_ _–_ C4K–I_/O_ _ C20P To order cable C4K–CN502 separately, specify (included with Unit) C4K–CN502...
  • Page 165 24 VDC 24 VDC, 32 pts. Relay with socket C60P–CDR–DE ––– Transistor, 1 A C60P–CDT1–DE ––– U: UL, C: CSA, N: NK See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1988).
  • Page 166 U, C 16 pts. 24 VDC ––– Relay with socket C16P–OR–D Transistor, 1 A C16P–OT1–D C20P Expansion 100 to 240 VAC 24 VDC, 12 pts. Relay with socket 8 pts. C20P–EDR–A U, C, N I/O Unit Transistor, 1 A C20P–EDT1–A Triac, 1A C20P–EDS1–A...
  • Page 167 24 VDC 24 VDC, 32 pts. Relay with socket C60P–EDR–D ––– Transistor, 1 A C60P–EDT1–D ––– U: UL, C: CSA, N: NK See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1988).

  • Page 168: Special Units

    ––– I/O Link Unit APF/PCF C20–LK011–P ––– C20–LK011 ––– I/OConnectingCable For horizontal mounting; cable length: 5 cm C20P–CN501 ––– (for maintenance) For vertical mounting; cable length: 40 cm C20P–CN411 ––– (for maintenance) I/OConnecting Cable For horizontal mounting; connects to Cable length: 5 cm C4K–CN502...
  • Page 169 Used to load programs in V8, M1R, M5R, POR, or S6 3G2A5–CMT01–E cassettes into the GPC and print them out through a Printer Interface Unit. U: UL, C: CSA, N: NK See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1988).
  • Page 170 Printer Connecting Cable 2 m (also used for X–Y plotter) SCY–CN201 ––– ––– Floppy Disk Interface Unit C20P/C28P/C40P. With comment file; able to connect to 3G2C5–FDI03–E NEC floppy disk controller Peripheral Interface Unit To connect GPC or FIT to P–type PCs 3G2C7–IP002–V2...
  • Page 171 Appendix B Programming Instructions A PC instruction is input either by inputting the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using func- tion codes. To input an instruction via its function code, press FUN, the function code, and then WRITE. Function code Name Mnemonic...

  • Page 172: Basic Instructions

    Programming Instructions Appendix B Basic Instructions Name Symbol Function Operands Mnemonic Load Used to start instruction line with status of des- ignated bit. Load NOT Used to start instruction line with inverse of LD NOT designated bit. Logically ANDs status of designated bit with execution condition.

  • Page 173: Special Instructions

    Appendix B Programming Instructions Name Symbol Function Operands Mnemonic Output Turns ON B for ON execution condition; turns OFF B for OFF execution condition. Output Turns OFF B for ON execution condition; turns ON B for OFF execution condition. OUT NOT Timer ON–delay (decrementing) timer operation.
  • Page 174 Programming Instructions Appendix B Name Symbol Function Operands Mnemonic Shift Creates a bit shift register from the starting St/E: Register word (St) through the ending word (E). I: SFT(10) input bit; P: shift pulse; R: reset input. St SFT(10) must be less than or equal to E and St and E must be in the same data area.
  • Page 175 Appendix B Programming Instructions Name Symbol Function Operands Mnemonic Move Transfers source data (S) (word or four–di- MOV(21) git constant) to destination word (D). MOV(21) Move NOT Inverts source data (S) (word or four–digit MVN(22) constant) and then transfers it to destina- tion word (D).
  • Page 176 Programming Instructions Appendix B Name Symbol Function Operands Mnemonic Set Carry Sets carry flag (i.e., turns CY ON). None STC(40) STC(40) Clear Carry CLC clears carry flag (i.e, turns CY OFF). None CLC(41) CLC(41) 4-to-16 Converts up to four hexadecimal digits in Decoder source word (S) into decimal values from 0 MLPX(76)

  • Page 177: Programming Console Operations

    Appendix C Programming Console Operations System Operations Operation/Description Modes* Key sequence Password Input R M P MONTR Controls access to the PC’s programming functions. To gain access to the system once “PASSWORD” has been displayed, press CLR, MONTR, and then CLR. Buzzer ON/OFF R M P SHIFT...
  • Page 178 Appendix C Programming Console Operations Programming Operations Operation/Description Modes* Key sequence Address Designation R P M Displays the specified address. [Address] Can be used to start programming from a non-zero address or to access an address for editing. Leading zeros need not be entered. The contents of the designated address will not be dislayed until the down key is pressed.
  • Page 179 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Program Check SRCH To check up to END(01) Once a program has been SRCH SRCH entered, it should be checked for errors. The address where To abort the error was generated will also be displayed.
  • Page 180 Appendix C Programming Console Operations Monitoring and Data Changing Operations Operation/Description Modes* Key sequence Bit/Word Monitor R P M Up to six memory addresses, CONT [Address] with either words or bits, or a SHIFT combination of the two, can be monitored at once.
  • Page 181 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Hex/BCD Data Change Bit/Hex [New Data] WRITE Used to edit the leftmost BCD monitor in progress or hexadecimal value displayed during a Bit/Word Monitor operation. If a timer or counter is leftmost on the display, the PV will be the value displayed and affected by this operation.
  • Page 182 Appendix C Programming Console Operations Operation/Description Modes* Key sequence 3-word Change This operation changes the 3-word Monitor [Data] WRITE value of a word displayed in progress during a 3-word monitor operation. The blinking cursor indicates the word that will be affected by the operation.
  • Page 183 Appendix C Programming Console Operations Operation/Description Modes* Key sequence Program Read Protect/Clear R P M [Mode changed] [4–digit number] Cleared WRITE RESET PLAY Protected WRITE Clear Forced Set/Reset PLAY Simultaneously clears all forced RESET bits within the word currently displayed. *Modes in which the given instruction is applicable: R = RUN, M = MONITOR, P = PROGRAM...
  • Page 184 Appendix C Programming Console Operations Cassette Tape Operations Operation/Description Modes* Key sequence Program Memory Save This operation copies data from [Start address] [File no.] WRITE the Program Memory to tape. The file no. refers to an identifying address for the information within the tape.
  • Page 185 Appendix C Programming Console Operations Operation/Description Modes* Key sequence DM Data Save, Restore, Compare 5 second leader tape The procedures for transferring DM area data to and from tape, and for comparing it, are Start tape recorder re- [File no.] SHIFT basically the same as for the cording.

  • Page 186: D - Error And Arithmetic Flag Operation

    Appendix D Error and Arithmetic Flag Operation The following table shows which instructions affect the ER, CY, GT, LT and EQ flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller;...

  • Page 187: E - Binary-Hexadecimal-Decimal Table

    Appendix E Binary–Hexadecimal–Decimal Table Decimal Binary 00000000 00000000 00000001 00000001 00000010 00000010 00000011 00000011 00000100 00000100 00000101 00000101 00000110 00000110 00000111 00000111 00001000 00001000 00001001 00001001 00010000 00001010 00010001 00001011 00010010 00001100 00010011 00001101 00010100 00001110 00010101 00001111 00010110 00010000 00010111 00010001 00011000...

  • Page 188: F - Word Assignment Recording Sheets

    Appendix F Word Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments on the Racks, as well as details of work bits, data storage areas, timers, and counters.
  • Page 189 I/O Bits Programmer: Program: Date: Page: Word: Unit: Word: Unit: Field device Notes Field device Notes Word: Unit: Word: Unit: Field device Notes Field device Notes...
  • Page 190 Work Bits Programmer: Program: Date: Page: Area: Word: Area: Word: Usage Notes Usage Notes Area: Word: Area: Word: Usage Notes Usage Notes...
  • Page 191 Data Storage Programmer: Program: Date: Page: Word Contents Notes Word Contents Notes...
  • Page 192 Timers and Counters Programmer: Program: Date: Page: T or Set value Notes T or Set value Notes address address...

  • Page 193: G - Program Coding Sheet

    Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, allowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands.
  • Page 194 Program Coding Sheet Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s) Address Instruction Operand(s)

  • Page 195: Glossary

    Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designate the word and/or bit location. For the UM area, an address designates the in- struction location (UM area);...
  • Page 196 Glossary bit number A number that indicates the location of a bit within a word. Bit 00 is the right- most (least significant) bit; bit 15 is the leftmost (most significant) bit. buffer A temporary storage space for data in a computerized device. bus bar The line leading down the left and sometimes right side of a ladder diagram.
  • Page 197 Glossary data area An area in the PC’s memory that is designed to hold a specific type of data, e.g., the SR area is designed to hold flags and control bits. Memory areas that hold programs are not considered data areas. data area boundary The highest address available in a data area.
  • Page 198 Glossary error code A numeric code output to indicate the existence of and something about the nature of an error. Some error codes are generated by the system; other are defined in the program by the operator. exection condition The ON or OFF status under which an instruction is executed. The execution condition is determined by the logical combination of conditions on the same instruction line and up to the instruction being executed.
  • Page 199 Glossary Host Link System One or more host computers connected to one or more PCs through Host Link Units so that the host computer can be used to transfer data to and re- ceive data from the PC(s). Host Link Systems enable centralized manage- ment and control of a PC System.
  • Page 200 Glossary input The signal coming from an external device into the PC. Input often is used abstractly or collectively to refer to incoming signals. input bit A bit in the IR area that is allocated to hold the status of an input. input device An external device that sends signal(s) into the PC System.
  • Page 201 Glossary jump number A definer used with a jump that defines the points from which and to which a jump is to be made. ladder diagram (program) A form of program arising out of relay-based control systems that uses cir- cuit-type diagrams to represent the logic flow of programming instructions.
  • Page 202 Glossary nest Programming one jump within another jump, programming a call to a subrou- tine from within another subroutine, etc. NO input An input that is normally open, i.e., the input signal is considered to be pres- ent when the circuit connected to the input closes. noise interference Disturbances in signals caused by electrical noise.
  • Page 203 Glossary output The signal sent from the PC to an external device. Output often is used ab- stractly or collectively to refer to outgoing signals. output bit A bit in the IR area that is allocated to hold the status to be sent to an output device.
  • Page 204 Glossary Programming Console The simplest form or Programming Device available for a PC. Programming Consoles are available both as hand-held models and as CPU-mounting models. Programming Device A peripheral device used to input a program into a PC or to alter or monitor a program already held in the PC.
  • Page 205 Glossary reversible shift register A shift register that can shift data in either direction depending on a specified condition(s). right-hand instruction Another term for terminal instruction. rightmost (bit/word) The lowest numbered bits of a group of bits, generally of an entire word, or the lowest numbered words of a group of words.
  • Page 206 Unit In OMRON PC terminology, the word Unit is capitalized to indicate any prod- uct sold for a PC System. Though most of the names of these products end with the word Unit, not all do, e.g., a Remote Terminal is referred to in a col- lective sense as a Unit.
  • Page 207 Glossary unit number A number assigned to some Link Units and Special I/O Units to assign words and sometimes other operating parameters to it. watchdog timer A timer within the system that ensures that the scan time stays within speci- fied limits.

  • Page 208: Index

    Index ADD(30). See instruction set data areas components, 12 analog timer unit. See instruction set data memory area, 26 AND. See instruction set holding relay area, 26 and inverse − AND NOT. See instruction set internal relay area AND LD. See instruction set I/O bits available AND load.
  • Page 209 Index floppy disk interface unit. See peripheral devices ILC(03), 53 converting to mnemonic code, 120 use in branching, 37 JME(05), 55 JMP(04), 55 GPC. See peripheral devices KEEP(11) graphic programming console. See peripheral devices as a bit control instruction, 51 greater than flag.
  • Page 210 Index instructions, 106 combining p−rom writer. See peripheral devices AND and OR, 33 AND LD and OR LD, 109 peripheral devices, 6 controlling bit status factory intelligent terminal (FIT), 6 using DIFU(13) and DIFD(14), 50 standard models, 162 using KEEP(11), 41 , 51 floppy disk interface unit, 6 using OUT and OUT NOT, 40 , 49 graphic programming console (GPC), 6...
  • Page 211 Index standard models TR bits DIN units, 162 converting to mnemonic code, 119 factory intelligent terminal, 162 use in branching, 35 graphic programming console, 162 I/O units, 159 P−Type CPUs, 158 peripheral devices, 163 UM area. See program memory special units, 161 units status indicators.

This manual is also suitable for:

Sysmac c28pSysmac c40pSysmac c60p

Table of Contents