Circuit - Brother HL-2400C Service Manual

2.3.2

Circuit

(1) CPU block
• Model name:
• Clock speed:
• Cache memory: 8KB (Command cache) / 8KB (Data cache)
• Appearance:
(2) ASIC block
• Model name:
• Appearance:
• Functions:
(3) ROM block
The ROM stores the CPU control program and font data. ROMs used are an
8Mbytes masked ROM, and a 2 Mbytes flash ROM which can be rewritten on
the board.
<Masked ROM>
• Access time:
• Appearance:
<Flash ROM>
• Model name:
• Access time:
• Appearance:
(4) DRAM block
DRAMs are used for the receiving buffer and the working area of the CPU.
The DRAM block contains eight 16Mbit EDO RAM, thus having 16MB
memory capacity in total.
• Model name:
• Type:
• Access time:
• Appearance:
MB86832-100 (SPARC lite), RISC CPU manufactured by
Fujitsu
33.1776MHz (external) / 99.5328MHz (internal)
176-pin QFP
MF87F1610 manufactured by Fujitsu
240-pin QFP
∗ Controls CPU
∗ Controls memory
∗ Controls interrupts
∗ Timer
∗ External interfaces (Centronics, RS-232C, PCMCIA, MIO)
∗ Engine interface (Engine control, Video signal control)
∗ Supports Software
less than 120nsec.
42-pin DIP
MBM29F800T-120 manufactured Fujitsu
less than 120nsec.
48-pin TSOP
M5M41705CJ-6 manufactured Mitsubishi (or equivalent).
16Mbit EDO DRAM (4x4, 164,304bit)
less than 80nsec.
26-pin SOJ
IV-47