Circuit Description - Acer AC511 SERIES Service Manual

Color monitor

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5-1 MICRO CONTROLLER CIRCUIT

MICRO Controller

The IC101 contains a 6502 8-bit CPU core,256 bytes of RAM, 16K bytes of ROM,14 channel 8 bit PWM D/A

converters, 2 channel A/D converters for key detection, one 8 bit pre-loadable

V-sync signals processor providing mode detection, watch- dog timer preventing system from abnormal operation,

and an I

C bus interface.

H/V sync signals processor

The functions of the sync processor include polarity detection, H-SYNC & V-SYNC signals counting,

Programmable SYNC signals output, free running signal generator. Pin39/Pin40 are for the H-SYNC and

V-SYNC input, Pin32/Pin33 will output the same signal as input sync signal without delay, and the polarity are

setting in the positive. When no signal input, the Pin32 will output a 61Hz V-SYNC free run signal. The Pin33

will output a 48KHz H-SYNC free run signal. for the monitor testing use.

On Screen Display Controller

The IC105 is designed for display the built-in characters or fonts onto monitor screen. The display operation is by

transforming data and control information from micro controller to RAM through a serial data interface.

Pin2 is used to control the internal oscillator frequency by DC voltage input from external low pass filter (R126,

C155) is used to regulate the appropriate bias current for internal oscillator the resonate at specific dot frequency.

Pin5 is input the horizontal fly back pulse, for PLL generator tracking.

Pin6 is left floating, I

Pin7 the external data transfer through this pin to internal display registers and control registers

Pin8 the clock-input pin is used to synchronize the data transfer.

Pin18 is input the vertical flyback pulse for synchronizing the vertical position.

Pin20 is output a blanking signal to cut off external R.G.B signals of VGA while this chip is displaying characters

or windows.

Pin21, Pin22, Pin23 is used to output the OSD (B.G.R) video signal.

5. CIRCUIT DESCRIPTION

C bus is enabled. Otherwise the SPI bus is enabled.

base timer, internal H-sync and

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