Kenwood TK-280 Service Manual page 18

TK-280
attached, MSW is connected to GND at inside of SP-MIC. For
this reason, Q300 is turned OFF, the internal microphone is
muted, and only the input of the external microphone is supplied
to the microphone amplifier of the TX-RX unit.
The signal from microphone passes through the limitter
circuit in D8, and Mic mute switch (Q17 is off in TX) and through
the high-pass filter, the ALC circuit, the low-pass filter, the high-
pass filter, and pre-emphasis/IDC circuit in IC13. When
encoding DTMF, mute switch (Q13) is turned OFF for muting
the microphone input signal.
The signal passes through the D/A converter (IC8) for the
maximum deviation adjustment, and enters the summing
amplifier consisting of IC7 (1/2), and is mixed with the low speed
data from the CPU (IC19) and 9600bps DATA from Optional
Board Terminal.
The output signal from the summing amplifier passes
through the D/A converter (IC8) again and goes to the VCO
modulation input.
The other output signal from the summing amplifier passes
through the D/A converter (IC8) again for the BAL adjustment,
and the buffer amplifier (IC1 : 2/2), and goes to the VCXO
modulation input.
EXT.
MIC
Q300 D8
MIC
12
SW LIMIT
MIC
Q17
MIC
MUTE
Q301
MSW PTT
Fig. 7 Microphone amplifier
4-2. Drive and Final amplifier
The signal from the T/R switch (D9 is on) is amplified by
drive amplifier (Q20) to 30mW.
The output of the drive amplifier is amplified by the RF power
amplifier (IC100) to 5.0W (1W when the power is low). The RF
power amplifier consists of two stages MOS FET transistor.
The output of the RF power amplifier is then passed through
the harmonic filter (LPF) and antenna switch (D12 is on) and
applied to the antenna terminal.
Q20
From
DRIVE
T/R SW
AMP
(D9)
+B
R244
R246
R248
IC23
(1/2)
REF
VOL
(IC8)
Fig. 8 Drive and final amplifier and APC circuit
18
CIRCUIT DESCRIPTION
MUTE DTMF
Q13
SW
IC13 15 16 18 19 9
HPF ALC COMP LPF HPF
IC8 IC7 (1/2) IC8
D/A D/A
SUM
VCO
I5 O5 AMP I2 O2
IC8 IC1
LSD DI9
D/A
BUFF
I1 O1 AMP
IC100
D12
RF
ANT
LPF
POWER AMP
SW
VDD VGG
IC23
(2/2)
4-3. APC circuit
The APC circuit always monitors the current flowing through
the RF power amplifier (IC100) and keeps a constant current.
The voltage drop at R244, R246 and R248 is caused by the
current flowing through the RF power amplifier and this voltage
is applied to the differential amplifier (IC23 1/2).
IC23(2/2) compares the output voltage of IC23(1/2) with
the reference voltage from IC8, and the output of IC23(2/2)
controls the VGG of the RF power amplifier to make the both
voltages to same voltage.
The change of power high/low is carried out by the change
of the reference voltage. Q22,23 and 25 are turned on in
transmit and the APC circuit is active.
5. Frequency Synthesizer Unit
5-1. Frequency synthesizer
The frequency synthesizer consists of the VCXO (X1), VCO
(A1), PLL IC(IC14) and buffer amplifiers.
The VCXO generates 16.8MHz. The frequency stability is
1.5ppm within the temperature range of -30 to +60˚C. The
frequency tuning and modulation of the VCXO are done to
apply a voltage to pin 1 of the VCXO. The output of the VCXO
is applied to pin 8 of the PLL IC.
8 The TK-280's VCO consists of 2VCO and covers a dual
6
PRE range of the 190.85~218.85MHz (K,K3,M), 186.85~206.85MHz
IDC
EMP
(K2,K4) and the 146~174MHz (K,K3,M), 136~162MHz (K2,K4).
The VCO generates 190.85~218.85MHz (K,K3,M),
A1
186.85~206.85MHz (K2,K4) for providing to the first local signal
in receive. In TX, the pin 3 of the VCO goes low and the VCO
X1
generates 146~174MHz (K,K3,M), 136~162MHz (K2,K4).
VCXO
The output of the VCO is amplified by the buffer amplifier
(Q16) and routed to the pin 5 of the PLL IC. Also the output of
the VCO is amplified by the buffer amplifier (Q18) and routed
to the next stage according to T/R switch (D9, D23).
The PLL IC consists of a prescaler, fractional divider,
reference divider, phase comparator, charge pump. This PLL
IC is fractional-N type synthesizer and performs in the 40, 50
or 60kHz reference signal which is eighth of the channel step
(5, 6.25 or 7.5kHz). The input signal from the pins 5 and 8 of
the PLL IC is divided down to the 40, 50 or 60kHz and compared
at phase comparator. The pulsed output signal of the phase
comparator is applied to the charge pump and transformed
into DC signal in the loop filter (LPF). The DC signal is applied
ANT
to the pin 1 of the VCO and locked to keep the VCO frequency
constant.
PLL data is output from DT (pin 75). CP (pin 19) and EP
(pin 47) of the microprocessor (IC19). The data are input to
the PLL IC when the channel is changed or when transmission
is changed to reception and vice versa. A PLL lock condition
is always monitored by the pin 31 (UL) of the microprocessor.
When the PLL is unlocked, the UL goes low.