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1.4
IC BLOCK DIAGRAM
1.4.1 IC 1002 (CXD2497R)
14
12
OSCI
28
OSCO
27
CKI
26
CKO
25
MCKO
30
1/2
SNCSL
3
Selctor
SSI
31
SCK
32
Register
SEN
33
SSGSL
6
SSG
RST
2
TEST1
37
TEST2
48
7
29
1
Pin Descriptions
Pin No. Pin Name I/O
Description
1
V
1
-
GND
SS
2
RST
I
System reset input terminal H: Reset released L: Reset
activated
(Should be activated at power ON, normally.)
(Schmitt trigger input/without protection diode on power
supply side)
3
SNCSL
I
Sync system switching control input terminal
(with pull-down resistor)
H: CKI sync L: MCKO sync
4
ID
O
Line identification pulse output terminal in the vertical
direction
5
WEN
O
Memory write timing pulse output terminal
6
SSGSL
I
Built-in SSG enable input terminal (with pull-down
resistor)
H: Built-in SSG is effective. L: External sync is effective.
7
V
1
-
3.3V power (for common logic section)
DD
8
V
2
-
3.3V power (for RG terminal)
DD
9
RG
O
Reset gate pulse output terminal for CCD
10
V
2
-
GND
SS
11
V
3
-
GND
SS
12
H1
O
Clock output terminal for CCD horizontal register
13
H2
O
Clock output terminal for CCD horizontal register
14
V
3
-
3.3V to 5.0V power (for H1 and H2 terminals)
DD
15
V
4
-
3.3V power (for CDS system terminals)
DD
16
XSHP
O
CCD pre-charge level sample/hold pulse output terminal
17
XSHD
O
CCD data level sample/hold pulse output terminal
18
XRS
O
Sample/hold pulse output terminal for phase matching in
analog-to-digital conversion
19
PBLK
O
Pulse output terminal for pulse cleaning during
horizontal and vertical blanking period
20
CLPDM
O
Pulse output terminal for CCD dummy signal clamping
21
V
4
-
GND
SS
22
OBCLP
O
Pulse output terminal for CCD optical black signal
23
ADCLK
O
Clock output terminal for analog-to-digital conversion IC
Logical phase is adjustable with the serial interface data
13
11
8
9
10
15
16
17
18
21
19
PBLK
20
CLPDM
22
OBCLP
Pulse Generator
23
ADCLK
24
V
SS
5
4
ID
5
WEN
Latch
41
V1A
43
V1B
39
V2
44
V3A
46
V3B
V Driver
40
V4
47
SUB
VH
42
VM
38
VL
45
36
35
34
24
V
5
-
GND
SS
25
CKO
O
Inverter output terminal
26
CKI
I
Inverter input terminal
27
OSCO
O
Inverter output terminal for oscillation (If not used,
should be opened or connected to GND through a
capacitor.)
28
OSCI
I
Inverter input terminal for oscillation (If not used, should
be fixed to "Low".)
29
V
5
-
3.3V power (for common logic section)
DD
30
MCKO
O
System clock output terminal for signal processing IC
31
SSI
I
Serial interface data input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
32
SCK
I
Serial interface clock input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
33
SEN
I
Serial interface strobe input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
34
VD
I/O
Vertical sync signal input/output terminal
35
HD
I/O
Horizontal sync signal input/output terminal
36
V
6
-
GND
SS
37
TEST1
I
IC test terminal 1 with pull-down resistor (Should be
fixed to GND normally.)
38
VM
-
GND (for vertical drivers)
39
V2
O
Clock output terminal for CCD vertical register
40
V4
O
Clock output terminal for CCD vertical register
41
V1A
O
Clock output terminal for CCD vertical register
42
VH
-
15.0V power (for vertical drivers)
43
V1B
O
Clock output terminal for CCD vertical register
44
V3A
O
Clock output terminal for CCD vertical register
45
VL
-
-7.5V power (for vertical drivers)
46
V3B
O
Clock output terminal for CCD vertical register
47
SUB
O
Pulse output terminal for CCD electronic shutter
48
TEST2
I
IC test terminal 2 with pull-down resistor (Should be
fixed to GND normally.)
1.4.2 IC 2001 (CDS/AGL)
ADCIN
27
CDSSW
25
CDSIN
26
BLKSH
28
DC offset
BLKFB
29
compensatory
17
Pin Descriptions
Pin No. Pin Name
Description
1
NC
No internal connection
2
D0
Digital output terminal (LSB)
3-10
D1-D8
Digital output terminals
11
D9
Digital output terminal (MSB)
12
NC
No internal connection
13
OADCLK Latch clock output terminal for D0 to D9
14
DV
Digital GND (0V)
SS
15
DV
Power for digital 3.0V system
DD
(Should be connected to AV
outside the IC.)
DD
16
ADCLK
Analog-to-digital conversion clock input terminal I
17
OBP
Optical black pulse input terminal
18
SPBLK
Black level sampling clock input terminal
19
SPSIG
Signal level sampling clock input terminal
20
PBLK
Pre-blanking signal input terminal
21
OADSW
OADCLK enable input terminal
22
AV
Analog GND (0V)
SS
23
AV
Power for analog 3.0V system
DD
24
NC
No internal connection
25
CDSSW
Signal level sampling output terminal
26
CDSIN
CDS input terminal
27
ADCIN
ADC input terminal
28
BLKSH
Black level sample/hold terminal
29
BLKFB
Black level feedback terminal
30
AV
Analog GND (0V)
SS
31
AV
Power for analog 3.0V system
DD
(Should be connected to DVDD outside the IC.)
32
VRT
Reference voltage terminal 3
(Ceramic capacitor of 0.1µF or more should be
connected between this terminal and AVss.)
33
VRB
Reference voltage terminal 2
(Ceramic capacitor of 0.1µF or more should be
connected between this terminal and AVss.)
1-7
1-6
21
13
16 18 19
41 46 40 48
TIMING
42 OEB
gen
11 D9
10 D8
10bit
CDS
PGA
9 D7
ADC
8 D6
Output
Latch
7 D5
circuit
6 D4
5 D3
4 D2
Serial
Bias
Interface
Occurrence
3 D1
2
20
44
45
43
35
33
34
32
34
VRM
Reference voltage terminal 1
Analog (A) or
I/O
Digital (D)
(Ceramic capacitor of 0.1µF or more should
be connected between this terminal and AVss.)
-
-
35
BIAS
Internal bias terminal
O
D
(A 24-Kohm resistor should be connected
O
D
between this terminal and AVss.)
O
D
36
NC
No internal connection
-
-
37
AV
Analog GND (0V)
SS
O
D
38
AV
Power for analog 3.0V system
DD
-
D
(Should be connected to DV
-
D
39
NC
No internal connection
40
AV
Analog GND (0V)
SS
D
41
AV
Power for analog 3.0V system
DD
I
D
(Should be connected to DV
I
D
42
OEB
Digital output enable control input terminal
I
D
43
CS
Serial interface control input terminal
I
D
44
SCK
Serial clock input terminal
I
D
45
SDATA
Serial data input terminal
-
A
46
DV
Power for digital 3.0V system
DD
(Should be connected to AV
-
A
47,48
DV
Digital GND
SS
-
-
O
A
I
A
I
A
-
A
-
A
-
A
-
A
-
A
-
A
D0
-
A
-
A
-
-
-
A
-
A
outside the IC.)
DD
-
-
-
A
-
A
outside the IC.)
DD
I
D
I
D
I
D
I
D
-
D
outside the IC.)
DD
-
D
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