Schematic Diagrams - Yamaha RX-V363 Service Manual

A B C

SCHEMATIC DIAGRAMS

DSP 1/6
1
2
EEPROM
3
3.4 3.4
0.4 3.4
3.4
3.3
0 3.4
4
to DSP 5/6
to DSP 6/6
5
to DSP 3/6
6
to DSP 5/6
7
to DSP 4/6
to DSP 2/6
to DSP 3/6, 4/6
8
to DSP3/6
9
10
D E F
to DSP 2/6
0
0
0
2.0
MICROPROCESSOR
2.0
3.4
0
0
0
B-2
1.7
1.9
3.4
3.4
0
0
0
0
3.4
1.5
3.4
3.4
0.2
0
3.4
0.2
0.6
3.4
1.8
0
0
3.2
0
0
0
0
0
0
DIGITAL OUT
POINT B-2 XL101 (Pin 11 of IC101)
G H I
0 0
0
0
0
0
0
and
0
0
DSP 0
0
0.2
0.2
0
0.3
0.3
0.3
0.3
0.3
1.5
0.3
0.3
IC101
0.6
3.4
0
1.7
1.7
1.7
1.6
1.6
1.6
1.6
1.6
0
3.4
0
0.2
3.4
0
0
0
0 0
AD IN DIGITAL IN
IC101: ADSP-BF531 CPU
Microprocessor
JTAG test Event controller/
Core timer Watch dock timer
and emulation
Voltage Real time clock
regulator
UART port IrDA®
Memory
L1 order L1 data
management
memory memory
unit
Timer0, Timer1, Timer2
Core/System bus interface
PPI/GPIO
DMA controller
Serial port (2)
SPI port
Boot ROM
External port for flash
and SDRAM control
J K L
1.5
1.5 1.5
3.4 3.4
3.4
1.5
2.0
1.5
to DSP 5/6
to DSP 2/6
to DSP 6/6
to DSP 5/6
IC102: BR25L320F-W EEPROM
SPI BUS 32 k-bit (4,096 x 8-bit) EEPROM
CS 1 VOLTAGE 8 Vcc
INSTRUCTION DECODE DETECTION
CONTROL CLOCK
GENERATION
WRITE HIGH VOLTAGE
SO 2 INHIBITION GENERATOR 7 HOLD
INSTRUCTION
REGISTER
STATUS REGISTER
WP 3 6 SCK
ADDRESS ADDRESS
12bit 12bit
REGISTER DECODER
32,768bit
EEPROM
DATA READ/WRITE
8bit 8bit
REGISTER AMP
GND 4 5 SI
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
M N
RX-V363/HTR-6130
73