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Sanyo DC-M3 Service Manual page 38

Separate mini component system
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IC BLOCK DIAGRAM & DESCRIPTION
IC102 LC78622NE (Digital Signal Processor)
EFMO
9
1
Slice level
DEFI
Control
10
EFMIN
Syncrnous Detect
22
FSEQ
EFM Demodulation
12
CLV+
CLV
Digital Servo
13
CLV-
14
V/P
PW
49
SBCK
51
Subcode Dxract
QCRC
47
SBSY
50
SFSY
63
CS
53
WRQ
COM
Inter Fase
SQOUT
55
CQCK
57
56
COIN
Servo Commander
54
RWC
15 16
17
HFL
TES
TOFF
No.
Pin Name
I/O
1
DEFI
I
Input terminal for detect signal of defect
2
TAI
I
Input terminal for test.
3
PDO
O The phase comparison output terminal for
external VCO control.
4
VVSS
- Ground terminal for built-in VCO
5
ISET
I
Resistance connection terminal for
electric current adjustment of PDO output.
6
VVDD
- Built-in VCO power supply terminal.
7
FR
I
VCO frequency range adjustment.
8
VSS
- Ground for Digital
9
EFMO
O EFM signal output terminal for slice level control.
10
EFMIN
I
EFM signal input terminal for slice level control.
11
TEST2
I
TEST pin. Normal time is non connection.
12
CLV+
O Output terminal for Disc motor control.
13
CLV-
O Output terminal for Disc motor control.
14
V/P
O Change of rough servo / phase control
Rough servo : "H", Phase control : "L"
15
HFL
I
Input terminal of track search signal.
16
TES
I
Input terminal of tracking error signal.
17
TOFF
O Output terminal of tracking off.
18
TGL
O Output terminal for change of tracking gain.
19
JP+
O Output terminal for tracking jump control.
20
JP-
O Output terminal for tracking jump control.
21
PCK
O Clock monitor output terminal for EFM data
playback. (4.3218 MHz)
22
FSEQ
O Output terminal for detect of SYNC signal.
23
DVDD
- +5V
24
CONT1
I/O
25
CONT2
I/O This output can control at serial control from
26
CONT3
I/O micro processor.
27
CONT4
I/O
28
CONT5
I/O
29
EMPH
O Output terminal of de-emphasis monitor .
"H" : de-emphasis
30
C2F
O Output terminal of C2 flag
31
DOUT
O Output terminal of digital out
32
TEST3
I
Test pin.
VV
VV
PDO ISET FR
DD
SS
6
4
3
5
7
VCO Clock Oscillator
& Clock Control
General Ports
20
19 58
18
24 25 26 27 28
JP-
JP+
RES
TGL
CONT1
CONT3
CONT5
EMPH
CONT2
CONT4
Function
TST11
TEST2
TEST4
PCK
TAI
TEST1
TEST3 TEST5
V
DD
21
2
59 64 11 32 33 62
23
2K~8bit
RAM
C1 C2 Error Detect &
Correct Control Flag
X'tal Root
Timing Generator
29
48
60 61 46 52 45 44 43
EFLG
16M
4.2M
FSX
XIN
XV
DD
RV
XV
XOUT
SS
No.
Pin Name
I/O
33
TEST4
I
34
NC
- Non connection.
35
MUTEL
O Mute output terminal for L-ch
36
LVDD
- Power supply for L-ch
37
LCHO
O Output terminal for L-ch
38
LVSS
- GND for L-ch
39
RVSS
- GND for R-ch
40
RCHO
O Output terminal for R-ch
41
RVDD
- Power supply for R-ch
42
MUTER
O Mute output terminal for R-ch
43
XVDD
- Power supply of crystal oscillation
44
XOUT
O Connection terminal of crystal oscillation (16.9344MHz)
45
XIN
I
46
XVSS
- GND of crystal oscillation
47
SBSY
O Output terminal for synchronizing signal of
48
EFLG
O Output terminal for correction monitor of C1, C2,
49
PW
O Output terminal for sub-cord of P, Q, R, S, T, U and W
50
SFSY
O Output terminal for synchronizing signal of
51
SBCK
I
52
FSX
O Output terminal of Synchronizing signal (7.35kHz)
53
WRQ
O Output terminal for standby of sub-cord Q output
54
RWC
I
55
SQOUT
O Output terminal of sub-cord Q
56
COIN
I
57
CQCK
I
58
RES
I
59
TST11
O Test pin
60
16M
O 16.9344MHz
61
4.2M
O 4.2336MHz
62
TEST5
I
63
CS
I
64
TEST1
I
- 16 -
V
SS
8
RAM Address
Generatorl
Interpolalation Mute
Billingual
Digital Out
Digital Attenuator
Quadruple Over Sampling
Digital Filter
1bit DAC
L.P.F
39 41 42
40
37
35
38
36
RV
RCHO
LCHO
MUTEL
LV
DD
DD
SS
MUTER
LV
SS
Function
Test pin.
Connection terminal of crystal oscillation (16.9344MHz)
sub-cord block
Single and Double
sub-cord frame
Input terminal for readout clock of sub-cord
Input terminal of read / write control
Input terminal of command from micro processor
Clock input for reading sub-cord from SQOUT
Reset (turn on : L)
Test pin
Chip select terminal
Test pin
30
C2F
31
DOUT
(NC)
34

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