Sony HCD-RV990D Service Manual page 114

HCD-RV660D/RV990D
• IC207 ZIVA5X-C1F (DVD SYSTEM PROCESSOR) (DMB03 Board (7/8))
Pin No. Pin Name
1 VDDP
2 HA1
3 to 11 HAD15 to HAD7
12 VDDP
13 GNDP
14 to 19 HAD6 to HAD1
20 VDDP
21 GNDP
22 HAD0
23 HDTACK
24 HIRQ0
25 WEH.UDS
26 WEL.LDS
27 HREAD
28 GPIO0(1)
29 GND
30 VDD
31 GND25
32 VDD25
33 to 42 MA9 to MA0
43 GND25
44 VDD25
45, 46 MA10, MA11
47, 48 BA1, BA0
49 MCS0
50 MCS1
51 MRAS
52 MCAS
53 MWE
54 GND25
55 VDD25
56 MCLK
57 to 60 MD0 to MD3
61 GND25
62 MDQM0
63 VDD25
64 to 71 MD4 to MD11
72 GND25
73 MDQM1
74 VDD25
75 to 78 MD12 to MD15
79 GND
80 VDD
81 to 84 MD16 to MD19
85 GND25
86 MDQM2
87 VDD25
88 to 95 MD20 to MD27
96 GND25
97 MDQM3
98 VDD25
99 to 102 MD28 to MD31
26
I/O
— Power supply pin (+3.2 V) (I/O signal)
I/O Address bus signal input from/output to bus interface IC.
I/O Data bus (address signal multiplexed) signal input from/output to bus interface IC.
— Power supply pin (+3.2 V) (I/O signal)
— Ground (I/O signal)
I/O Data bus (address signal multiplexed) signal input from/output to bus interface IC.
— Power supply pin (+3.2 V) (I/O signal)
— Ground (I/O signal)
I/O Data bus (address signal multiplexed) signal input from/output to bus interface IC.
I/O Not used (Fixed at H)
I Not used (Fixed at H)
I/O Host upper data strobe signal input from/output to programmable ROM IC.
I/O Not used (Open)
I/O Read/write strobe signal input from/output to programmable ROM IC.
I/O Jig detection port
— Ground (inside core)
— Power supply pin (+1.8 V) (inside core)
— Ground (SDRAM I/O signal)
— Power supply pin (+3.2 V) (SDRAM I/O signal)
O SDRAM address bus signal output to 128 Mbit SD-RAM IC.
— Ground (SDRAM I/O signal)
— Power supply pin (+3.2 V) (SDRAM I/O signal)
O SDRAM address bus signal output to 128 Mbit SD-RAM IC.
O SDRAM bank select signal output to 128 Mbit SD-RAM IC.
O SDRAM chip select signal output to 128 Mbit SD-RAM IC.
O Not used (Open)
O SDRAM row address strobe signal output to 128 Mbit SD-RAM IC.
O SDRAM column address strobe signal output to 128 Mbit SD-RAM IC.
O SDRAM write enable signal output to 128 Mbit SD-RAM IC. (H: read, L: write)
— Ground (SDRAM I/O signal)
— Power supply pin (+3.2 V) (SDRAM I/O signal)
O SDRAM clock signal output to 128 Mbit SD-RAM IC.
I/O SDRAM data input from/output to 128 Mbit SD-RAM IC.
— Ground (SDRAM I/O signal)
O Byte read/write mask signal output to 128 Mbit SD-RAM IC.
— Power supply pin (+3.2 V) (SDRAM I/O signal)
I/O SDRAM data input from/output to 128 Mbit SD-RAM IC.
— Ground (SDRAM I/O signal)
O Byte read/write mask signal output to 128 Mbit SD-RAM IC.
— Power supply pin (+3.2 V) (SDRAM I/O signal)
I/O SDRAM data input from/output to 128 Mbit SD-RAM IC.
— Ground (inside core)
— Power supply pin (+1.8 V) (inside core)
I/O SDRAM data input from/output to 128 Mbit SD-RAM IC.
— Ground (SDRAM I/O signal)
O Byte read/write mask signal output to 128 Mbit SD-RAM IC.
— Power supply pin (+3.2 V) (SDRAM I/O signal)
I/O SDRAM data input from/output to 128 Mbit SD-RAM IC.
— Ground (SDRAM I/O signal)
O Byte read/write mask signal output to 128 Mbit SD-RAM IC.
— Power supply pin (+3.2 V) (SDRAM I/O signal)
I/O SDRAM data input from/output to 128 Mbit SD-RAM IC.
Pin Description