Main Pcb; Cpu - Brother HL-2030 Service Manual

1.3

Main PCB

For the entire circuit diagram of the main PCB, see
DIAGRAM' in this manual.
1.3.1

CPU

A Fujitsu 32bit RISC CPU, SPARClite is built in the ASIC. While the CPU is driven with a clock
frequency of 48.00 MHz (HL-2030/2040) or 66.66 MHz (HL-2070N) in the user logic block, it
itself runs at 96.0 (HL-2030/2040) or 133.0 MHz (HL-2070N), which is generated by multiplying
the source clock by two.
< HL-2030/2040 >
If=(3.3V-1.2V)/180
P=(11.7mA)^2*180
=1/41W
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DATA[15-0]
5C
TP116
C76
R86
330
1
C5P
48.00MHz
X2
XTAL
C75 2
0V
AT-49 48.00MHZ
C5P
@C16
1
C10P
@X1
@C11 2
0V
AT-49 33.333333MHZ
0
33.3333MHz
XTAL
USBVCC
R28 1k
VDD3
DBRXD
2D
HTLIMITN
SCANNER_FGS
MAIN_FGS2
VDD3 VDD3
FRONT_COVER_SEN
R114
R115
REG_REAR_SEN
180
33k
REG_FRONT_SEN
=11.7mA
TP141 PI1
PEDG_SEN
TP97
A
C
Ic=3.3V/33k
=97 A
E
TNRLED
K
SG-206S
0V
GRIDC
EJECT SENSOR
THM1
2-2B
TNR_SEN
FB_TR
FB_TRCCV
FB_GRID
FB_DEV
FB_VCLN
SENSE
2-5B/2-7B
APPENDIX 1. to 6. 'MAIN PCB CIRCUIT
U4
TP63
138 111
DATA00 ADR1
TP62
139 112
DATA01 ADR2
TP61
140 113
DATA02 ADR3
TP67
141 116
DATA03 ADR4
TP60
142 117
DATA04 ADR5
TP66
143 118
DATA05 ADR6
TP59
2 119
DATA06 ADR7
TP81
3 120
DATA07 ADR8
TP94
4 121
DATA08 ADR9
TP120
5 122
DATA09 ADR10
TP123
6 123
DATA10 ADR11
TP96
8 124
DATA11 ADR12
TP103
9 125
DATA12 ADR13
TP111
10 126
DATA13 ADR14/BA0
TP108
11 130
DATA14 ADR15/BA1
TP112
12 131
DATA15 ADR16/RASN
132
ADR17/CASN
133
ADR18/WEN
134
ADR19/DQM0
135
ADR20/DQM1
31 136
UCKOUT ADR21
137
ADR22
R85
2.2k
29
UCKIN
0V
15
ROMCSN0
16
IOWEN
27 17
SCKIN IORDN
18
SDCLK0
0V
19
SDCSN0
TP17
@R20 85
VCKOUT
100
95
@R19
EESCL
8E
3.3k
94 7E
EESDA
87
VCKIN
5E
101
USBCTL
5E
98
USBDP
5E
102 99
USBVCC UDBDN
5E
TP5 TP4
82 83
DBRXD DBTXD
2D
80
VBDN VBDN
5D
81
VSH
2-2F
25 23
HTLIMITN HEATERON HEATERON
2-1A 24 2-1A
RLYOFFN RLYOFFN
2-1A
21
FAN24V FAN24V
22 2-6A
FAN12V FAN12V
2-6B
73 74
SCANFGS SCANCTL
2-6C
2-4D
(5Vtol)
35 34
DCFGS DCCTL
2-7E 33 2-7D
(5Vtol)
DCFR
(5Vtol) 2-7D
59 60
PNLSW0 PNLSW0 PNLLED0 PNLLED0
2-2F 61 2-2F
PNLLED1 PNLLED1
52 62 2-2F
SEN0 PNLLED2 PNLLED2
2-2F 2-2F
51 63
SEN1 PNLLED3 PNLLED3
2-2D 50 2-2F
SEN2
2-2B
49
SEN3
2-2B 20 48
SEN4 SOL1 SOL1
47 2-2E
SOL2 SOL2
2-3B
2-2E
53
TNRLED
69 67
HVNOISE HVVCLN TP42
2-2C
70
HVPWMVCLN HVPWMTRCV
68 2-2D
HVPWMDEV HVPWMVCLN
64 2-2D
HVPWMTRCV HVPWMDEV
TP182
L9 2-2D
39 65
AI0 HVPWMTRCC HVPWMTRCC
0 66 2-2D
HVPWMCHG HVPWMCHG
40 2-2D
ANALOG
AI1
2-2D
41
ANALOG
AI2
2-2C
72
REV1
42
ANALOG
AI3
TP32
2-2C
71
(5Vtol) PORT00
43 36
ANALOG
AI4 PORT01
(5Vtol)
TP89
2-2C 26
PORT02
(5Vtol)
TP31
ANALOG 44 75
AI5 PORT03
TP14
2-2C 104
PORT04
TP7
ANALOG 45 105
AI6 PORT05
(5Vtol)
TP1
2-2C 106
PORT06
(5Vtol)
TP181 TP2
L10
46 107
AI7 (5Vtol) PORT07
TP6
0 108
PORT08
Bellona
Fig. 3-3
3-3
HL-2030/2040/2070N SERVICE MANUAL
VDD3
TP113
ADR[1]
TP121
ADR[2]
TP127
ADR[3]
TP135
ADR[4]
TP133
ADR[5]
TP124
ADR[6]
TP117
ADR[7]
TP109
ADR[8]
TP95
ADR[9]
TP53
ADR[10]
TP44
ADR[11]
TP79
ADR[12]
TP46
ADR[13]
TP70
ADR[14]
TP87
ADR[15]
TP115
ADR[16]
TP92
ADR[17]
TP83
ADR[18]
TP131
ADR[19]
TP75
ADR[20]
TP102
ADR[21]
TP76
ADR[22]
ADR[22-1]
5C/6A/6B
TP100
ROMCSN0
TP106
7A
IOWEN
TP105
7A
IORDN
7A
TP91
SDCLK0
TP99
6B
SDCSN0
6A
EESCL
EESDA
USBCTL
USBDP
USBDN
DBTXD
PNEW_SEN
SCAN_CTL
MAIN_CTL
MAIN_F/R
R34
VDD3
TP189
10k
MAIN_FGS
2-8C
10k
R36
VDD3
MAIN_START
2-7C
10k
R73
VDD3
@R31
10k
VDD3
R7
10k
@R30
10k
0V
0V
R6 10k
VDD3
@R4
10k
0V
R3 10k
VDD3
R1 10k
0V
CDCC_RSTN
3-1B
CDCC_DATA
3-1C
CDCC_REQN
3-1C
CDCC_INTN
3-1B
CDCC_CLK
3-1C
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