Sanyo DC-X8CT Service Manual page 37

IC BLOCK DIAGRAM & DESCRIPTION
IC190 M38504M6H-230FP (Single Micro chip 8-bit)
Pin Name
Apply voltage of 2.7 - 5.5V to V
1 V
and 0V to V
CC
Reference voltage input pin for A-
2 V
D converter.
REF
3 AV Connect V
SS
4 P4 /INT /PWM
4 3
5 P4 /INT 8-bit CMOS I/O port with the
3 2
6 P4 /INT same function as port P0.
2 1
7 P4 /INT CMOS compatible input level.
1 0
8 P4 /CNTR CMOS 3-state output structure.
0 1
I/O direction register allows each
9 P2 /CNTR
7 0/
pin to be individually
S
RDY
programmed as either input or
10 P2 /S 8-bit CMOS I/O port.
6 CLK
CMOS compatible input level.
11 P2 /SCL /T D P2 , P2
5 2 X 0 1
12 P2 /SDA /R D state output structure.
4 2 X
P2 to P2
2
between CMOS compatible input
13 P2 /SCL
3 1
level or SMBUS input level in the
14 P2 /SDA
2 1
2
16 P2 /X I C-BUS interface function.
1 CIN
17 P2 /X P2 , P2
0 OUT 4 3
structure in the I
function.
P2 , P2
2 3
structure.
This pin controls the operation
15 CNV mode of the chip.
SS
Normally connected to V
18 RESET Reset input pin for active "L".
Input and output pins for the clock
generating circuit.
When an external clock is used,
19 X
IN
connect the clock source to the
X pin and leave the X
IN
open.
Connect a ceramic resonator or
quartz-crystal oscillator between
20 X
OUT
the X and X
IN
oscillation frequency.
Apply voltage of 2.7 - 5.5V to V
21 V
and 0V to V
SS
22 P1
7
23 P1
6
24 P1 8-bit CMOS I/O port.
5
25 P1 CMOS 3-state output structure.
4
I/O direction resister allows each
26 P1 pin to be individually
3
27 P1 programmed as either input or
2
28 P1 output.
1
29 P1 CMOS compatible.
0
30 P0 P1 to P1
7 3
31 P0 output large current for LED drive
6
32 P0 (M38513E4/M4).
5
33 P0 P1 to P1
4 0
34 P0 output large current for LED drive
3
35 P0 (M38514E6/M6)
2
36 P0
1
37 P0
0
38 P3 /AN
4 4
8-bit CMOS I/O port with the
39 P3 /AN
3 3
same function as port P0.
40 P3 /AN
2 2
CMOS compatible input level.
41 P3 /AN
1 1
CMOS 3-state output structure.
42 P3 /AN
0 0
Function
,
CC
.
SS
SS.
, P2 to P2 : CMOS 3-
4 7
can be switched
5
: N-channel open-drain
2
C-BUS interface
: N-channel open-drain
SS
pin
OUT
pins to set the
OUT
,
CC
.
SS
(5 bits) are enabled to
7
(8-bits) are enabled to
7
X V
X
IN OUT SS
19 20 21
Sub- Sub-
clock clock
input output
X X
CIN OUT
Ciock generating
circuit
R A M R O N
Watchdog
timer Reset
A-D PWM
converter (8)
(10)
INT -
0
INT
3
P4(5) P3(5)
2 3 4 5 6 7 8 38 39 40 41 42
IC103 LA6541 (Pick-up Actuator & Motor Driver)
Vcc Vref VIN4 VG4 Vo8
24 23 22 21 20
11k
Level BTL
Sift Driver
Level BTL
Sift Driver
11k
1 2 3 4 5
Vcc Mute VIN1 VG1 Vo1
IC131.IC132 TA7291S( Bridge Driver)
Vcc Vref
2 8
REG
Protective Circuit
(Heat Interception)
9 1
IN1 IN2
- 48 -
V CNV
RESET
CC SS
1 18 15
C P U
A
X
Y
S
CNTR
PC PC 0
H L
PS
2
SI/O(8) I C
XCOUT
XCIN
P2(8)
9 10 11 12 13 14 16 17
Vo7 GND Vo6 Vo5
19 18 17
Vcc
BTL
Driver
BTL
Driver
6 7 8
Vo2 GND Vo3 Vo4
5
GND
Timer 1(8)
Prescaler 12(8) Timer 2(8)
Prescaler X(8) Timer X(8)
Prescaler Y(8) Timer Y(8)
CNTR
1
P1(8) P0(8)
22 23 24 25 26 28 29 30 31 32 33 34 35 36 37
27
VG3 VIN3 CD RES
16 15 14 13
11k
Level
RESET
Sift
Level
Regulator
Sift
11k
9 10 11 12
VG2 VIN2 Reg OUT Reg IN
6 Vs
OUT1
7
3 OUT2