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System Control Block Diagram - Sony DVP-NS305 Service Manual

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DVP-NS305/NS310/NS315/NS405/NS410/NS415

3-4. SYSTEM CONTROL BLOCK DIAGRAM

MB-103 BOARD (3/4)
(SEE PAGE 4-25 to 4-28)
HA 0 – 21
HA 0 – 21
HD 0 – 15
HD 0 – 15
XRD
XWRH
SIGNAL PROCESSOR
(SEE PAGE 3-5)
XARPIT
XARPCS
XWAIT
XRST
XRST
XSDPIT
XSDPCS
RF/SERVO
XDRVMUTE
(SEE PAGE 3-4)
XLDON
CKSW1
OCSW1
XAVDIT
DREQ0
DACK0
DREQ1
DACK1
XAVDCS2
XAVDCS3
TRST
SIGNAL PROCESSOR
(SEE PAGE 3-5)
33MARP
27MAVD
512FSAVD
16
IC106
FLASH
1 – 5 102 – 109 111 – 118 120 85 – 100
58
HA 0 – 21
HD 0 – 15
70
XRD
71
XWRH
17
INT1
62
CS4X
67
XWAIT
35
XRST
18
INT2
63
CS5X
IC104
48
XDRVMUTE
82
WIDE
SYSTEM
CONTROL
56
CKSW1
57
OCSW1
IC101
EEPROM
WP
7
7
WP
SCL
6
39
SCL
SDA
5
38
SDA
16
INTO
46
DREQ0
47
DACK0
49
DREQ1
50
DACK1
60
CS2X
61
CS3X
81
IC103
PLL
3
IC103 qg
14
FSEL
5.0Vp-p
29.5nsec
15
33-1OUT
3
27-1OUT
3-7
5
IC104 tf
X1
53
X101
16.5MHz
X2
54
XARPRST
36
SI0
25
SO0
26
SCO
27
XIFCS
51
INT4
20
XFRRST
76
MAMUTE
83
SO1
29
SC1
30
XDACS
79
1
IC103 8
4.4Vp-p
37nsec
4
XTI
7
X102
27MHz
XTO
8
512-2OUT
9
512-1OUT
10
2
IC103 3
5.5Vp-p
37nsec
1.8Vp-p
60.6nsec
CN601 (2/3)
WIDE
SI0
SO0
SC0
XIFCS
IFBSY
TRST
MAMUTE
SO1
SC1
XDACS
AUDIO
(SEE PAGE 3-11)
XRST
IC103 9q;
5.0Vp-p
40.8nsec
512FS2CH
512FS6CH
3-8
VIDEO
2
WIDE
(SEE PAGE 3-9)
CN101
4
SI0
SO0
1
INTERFACE
3
SC0
CONTROL
6
XIFCS
(SEE PAGE 3-13)
XIFBUSY
5
8
XFRRST

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