Super I/O; Advanced Power Management; Intel ® Intelligent Power Node Manager (Nm) (Available When The Nmview Utility Is Installed In The System); Management Engine (Me) - Supermicro X9DRW-3F User Manual

Hide thumbs Also See for X9DRW-3F:
Table of Contents

Advertisement

X9DRW-3F/X9DRW-iF Motherboard User's Manual
filter to shield the computer from noise. It is recommended that you also install a
power surge protector to help avoid problems caused by power surges.
1-7

Super I/O

The Super I/O provides functions that comply with ACPI (Advanced Configuration
and Power Interface), which includes support of legacy and ACPI power manage-
ment through an SMI or SCI function pin. It also features auto power management
to reduce power consumption.
1-8

Advanced Power Management

The new advanced power management features supported by the motherboard
includes the following:
Intel
Intelligent Power Node Manager (NM) (Available
®
when the NMView utility is installed in the system)
The Intel
Intelligent Power Node Manager (IPNM) provides your system with
®
real-time thermal control and power management for maximum energy efficiency.
Although IPNM Specification Version 1.5/20 is supported by the BMC (Baseboard
Management Controller), your system must also have IPNM-compatible Manage-
ment Engine (ME) firmware installed to use this feature.
Note: Support for IPNM Specification Version 1.5 or Version 2.0 depends
on the power supply used in the system.

Management Engine (ME)

The Management Engine, which is an ARC controller embedded in the PCH, pro-
vides Server Platform Services (SPS) to your system. The services provided by
SPS are different from those provided by the ME on client platforms.
1-9

Introduction to the IPMI Controller

This motherboard incorporates the Renesas IPMI Controller, which integrates a
RISC (Reduced _Instruction_Set_Computing) CPU Core with peripheral capabili-
ties required for a Baseboard Management Controller (BMC). The Renesas IPMI
Controller offers the user a superb solution to manage PC server systems with
great efficiency.
The BMC controller supports a 32Kb_instruction cache and a 32Kb_operand cache,
which can be switched between write-back and write-through. The instruction cache
1-14

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

X9drw-if

Table of Contents