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shielded cables (see also cables) 1-4, 2-7
signal adaptations A-3
signal ground A-6
signal levels A-1
signals
transfer type (TT) 3-3
software initialization 3-30
software-programmable hardware inter-
rupts 4-8
specifications 1-3
SRAM (static RAM) 4-2
SRAM backup power source select head-
er J8 2-5
SRAM battery backup 4-2
SRST (system reset) 3-1, 3-30
static RAM (SRAM) 4-2
support information 1-8
SYSRESET* (see system reset) 3-1, 3-30
system considerations 2-7
system console terminal 1-6
system controller 2-2
system controller function 2-2, 3-30
system controller header J2 2-2
system mode 1-6
system reset (SRST) 3-30
system reset (SRST) (see SYSRESET*) 3-1
SYSTEM V/68 1-6
systems serial ID 3-28
T
terminal(s) A-1
terminology 1-9
tick timers 4-7
timeout 4-8
global bus 2-8
local bus 4-8
timers 4-7
timing performance 4-8
TOD clock memory map 3-26
transfer type (TT) signals 3-3
transition modules 1-5, 4-5
transparent mode A-4
MVME167/D3
TRXC4 (Transmit Receive Clock 4) 2-4
TT (transfer type) signals 3-3
U
unpacking instructions 2-1
V
VMEbus 3-29
VMEbus accesses to the local bus 3-29
VMEbus interface 4-4
VMEbus memory map 3-29
VMEbus short I/O memory map 3-29
VMEbus specification 1-8
VMEchip2 1-5
VMEchip2 GCSR (Global Control and
Status Registers) 2-8
VMEchip2 LCSR (Local Control and Sta-
tus Registers) 2-2
VMEchip2 memory map 3-8
W
warnings 4-3
watchdog timer 3-30, 4-8
word 1-9
I
N
D
E
X
IN-5
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