Last Buffer Address Register (Lbar); Octet Terminal Count Register(Otcr) - Motorola DragonBall MC68328 User Manual

LCD Controller
WS1-WS0 DMA Bursting Clock Control
Number of clock cycles per DMA word access
00 = Single clock-cycle transfer
01 = Two clock-cycle transfer
10 = Three clock-cycle transfer
11 = Four clock-cycle transfer
DWIDTH
Displays memory-data width indicating the size of the external bus interface.
0 = 16-bits memory
1 = 8-bits memory
PCDS Pixel Clock Divider Source Select
0 = The SYS CLK output of PLL is selected
1 = The PIX CLK output of PLL is selected

4.7.5.3 LAST BUFFER ADDRESS REGISTER (LBAR).

UNUSED
LBA7-LBA1
The number of memory words required to fill one line on the display panel. The count is
typically equal to the screen width in pixels divided by 16 for black-and-white display, or
by 8 if in gray scale. For panning, add one more count for black-and-white and two for gray
display.

4.7.5.4 OCTET TERMINAL COUNT REGISTER(OTCR).

OTC8-OTC1
Controls the time interval between two lines; therefore, the frame refresh rate can also be
finely adjusted. The register value must be greater than LBAR by 4 for black-and-white
display and 8 for gray display.
4-18 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
7 6 5
LBAR7 LBAR6 LBAR5
Address: $(FF)FFFA29
Figure 4-21. Last Buffer Address Register
7 6 5
OTC8 OTC7 OCT6 OCT5
Address: $(FF)FFFA2B
Figure 4-22. Octet Terminal Count Register
4 3 2
LBAR4 LBAR3 LBAR2
Reset Value: $3E
4 3 2 1
OTC4 OTC3 OTC2
Reset Value: $3F
1 0
LBAR1
0
OTC1
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